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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/H1 Series TMP92C820FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (INT0 to INT3, INTKEY, INTRTC, INTALM0 to INTALM4), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP92C820 CMOS 32-bit Microcontrollers TMP92C820FG/JTMP92C820 1. Outline and Device Characteristics TMP92C820 is high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. TMP92C820 is a microcontroller which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92C820FG is housed in a 144-pin flat package. JTMP92C820 is a 144-pad chip product. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H1 CPU) * * * * Compatible with TLCS-900, 900/L, 900/L1, 900/H's instruction code 16 Mbytes of linear address space General-purpose register and register banks Micro DMA: 8 channels (250 ns/4 bytes at fSYS = 20 MHz, best case) (2) Minimum instruction execution time: 50 ns (at SYS = 20 MHz) RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 021023_D 070208EBP * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 021023_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S 92C820-1 2007-02-16 TMP92C820 (3) Internal memory * * * * * * Internal RAM: 8 Kbytes (can use for code section) Internal ROM: None Expandable up to 136 Mbytes (Shared with program/data area) Can simultaneously support 8-/16-/32-bit width external data bus .... Dynamic data bus sizing Separate bus system Chip select outputs: 4 channels (4) External memory expansion (5) Memory controller (6) 8-bit timers: 4 channels (7) 16-bit timer/event counter: 1 channel (8) General-purpose serial interface: 3 channels * UART/synchronous mode * IrDA (9) Serial bus interface: 1 channel * I2C bus mode * Clock synchronous select mode (10) LCD controller * Shift register/built-in RAM LCD driver * * Supported 16, 8 and 4 gray-levels and black and white Hardware blinking cursor (11) SDRAM controller * Supported 16-M, 64-M and 128-Mbit SDRAM with 16-/32-bit data bus (12) Timer for real-time clock (RTC) * Based on TC8521A * Separate the power supply (13) Key-on wakeup (Interrupt key input) (14) 10-bit AD converter: 5 channels (15) Watchdog timer (16) Melody/alarm generator * Melody: Output of clock 4 to 5461 Hz * * Alarm: Output of the 8 kinds of alarm pattern Output of the 5 kinds of interval interrupt (17) MMU * Expandable up to 136 Mbytes (4 local areas/8 bank methods) (18) Interrupts: 45 interrupts * 9 CPU interrupts: Software interrupt instruction and illegal instruction * * 31 internal interrupts: Seven selectable priority levels 5 external interrupts: Seven selectable priority levels (4-edge selectable) 92C820-2 2007-02-16 TMP92C820 (19) Input/output ports: 83 pins (Except Data bus (16bit), Address bus (24bit) and RD pin) (20) Standby function * Three HALT modes: IDLE2 (Programmable), IDLE1, STOP (21) Triple-clock controller * Clock gear function: Select a high-frequency clock fc to fc/16 * RTC (fs = 32.768 kHz) (22) Operating voltage * DVCC = 3.0 to 3.6 V * RTCVCC = 2.0 to 3.6 V (23) Package * 144-pin QFP (P-LQFP144-1616-0.40C) * Chip form supply also available. For details, contact your local Toshiba sales representative 92C820-3 2007-02-16 TMP92C820 PG0 to PG4 (AN0 to AN4) ( ADTRG ) PG3 AVCC AVSS VREFH VREFL (TXD0) PF0 (RXD0) PF1 (SCLK0/ CTS0 ) PF2 (TXD1) PF3 (RXD1) PF4 (SCLK1/ CTS1 ) PF5 ( CS2G /TXD2) P95 ( CSEXA RXD2) P96 (SCK) P90 (SO/SDA) P91 (SI/SCL) P92 ( CS2E ) P93 ( CS2F ) P94 900/H1 CPU 10-bit 5-channel AD converter XWA XBC XDE Serial I/O SIO0 Serial I/O SIO1 Serial I/O SIO2 Serial bus I/F SBI0 Port 9 XHL XIX XIY XIZ XSP 32 bits SR PC F Port 0 Port 1 Port 2 Port 3 Watchdog timer Port 4 Port 5 MMU Port 6 W B D H IX IY IZ SP A C E L Mode controller Interrupt controller DVCC [3] DVSS [4] H-OSC Clock gear L-OSC XT1 XT2 RESET X1 X2 AM0 AM1 PC3 (INT0) D0 to D7 P10 to P17 (D8 to D15) P20 to P27 (D16 to D23) P30 to P37 (D24 to D31) P40 to P47 (A0 to A7) P50 to P57 (A8 to A15) P60 to P67 (A16 to A23) P70 ( RD ) P71 ( WRLL ) P72 ( WRLU ) P73 ( WRUL ) P74 ( WRUU ) P75 (R/ W ) P76 ( WAIT ) P80 ( CS0 / SDCSH ) P81 ( CS1 / SDCSL ) P82 ( CS2 / CS2A ) P83 ( CS3 ) P84 ( CS2B /EA24) P85 ( CS2C /EA25) P86 ( CS2D ) (TA0IN) PC0 8-bit timer (Timer 0) 8-bit timer (Timer 1) 8-bit timer (Timer 2) (TA1OUT/INT1) PC1 8-Kbyte RAM Port 7 (TA3OUT/INT2) PC5 8-bit timer (Timer 3) Port 8 16-bit timer (TB0OUT0/INT3) PC6 (D1BSCP) PK0 (D2BLP) PK1 (D3BFR) PK2 (DLEBCD) PK3 (DOFFB) PK4 PL0 to PL7 (LD0 to LD7) ( SDRAS ) PJ0 ( SDCAS ) PJ1 ( SRWR / SDWE ) PJ2 ( SRLLB /SDLLDOM) PJ3 ( SRLUB /SDLUDOM) PJ4 ( SRULB /SDULDOM) PJ5 ( SRUUB /SDUUDOM) PJ6 (SDCKE) PJ7 (SDCLK) P87 LCD controller Keyboard I/F RTC Melody/ alarm out PA0 to PA7 (KI0 to KI7) RTCVCC XT1/XT2/ BE ( ALARM / MLDALM /PK6) SDRAM controller Figure 1.1 TMP92C820 Block Diagram 92C820-4 2007-02-16 TMP92C820 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92C820, their names and functions are as follows: 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment of the TMP92C820FG. 0H 140 135 130 125 120 115 VREFL VREFH PG0/AN0 PG1/AN1 PG2/AN2 PG3/AN3/ADTRG PG4/AN4 PA3/KI3 PA4/KI4 PA5/KI5 PA6/KI6 PA7/AI7 PC0/TA0IN PC1/TA1OUT/INT1 PC5/TA3OUT/INT2 PC6/TB0OUT0/INT3 PF0/TXD0 PF1/RXD0 PF2/SCLK0/CTS0 PF3/TXD1 PF4/RXD1 PF5/SCLK1/CTS1 PL0/LD0 PL1/LD1 PL2/LD2 PL3/LD3 PL4/LD4 PL5/LD5 PL6/LD6 PL7/LD7 PK0/D1BSCP PK1/D2BLP PK2/D3BFR PK3/DLEBCD PK4/DOFFB PK6/ALARM/MLDALM 1 110 AVCC AVSS PA2/KI2 PA1/KI1 PA0/KI0 PJ7/SDCKE PJ6/SDUUDQM/SRUUB PJ5/SDULDQM/SRULB PJ4/SDLUDQM/SRLUB PJ3/SDLLDQM/SRLLB PJ2/SDWE/SRWR PJ1/SDCAS PJ0/SDRAS P96/CSEXA/RXD2 P95/CS2G/TXD2 P94/CS2F P93/CS2E P92/SI/SCL P91/SO/SDA P90/SCK P87/SDCLK P86/CS2D P85/EA25/CS2C P84/EA24/CS2B P83/CS3 P82/CS2/CS2A P81/CS1/SDCSL DVSS4 P80/CS0/SDCSH P76/WAIT P75/RW P74/WRUU P73/WRUL P72/WRLU P71/WRLL P70/RD 105 5 100 10 15 TMP92C820FG QFP144 95 90 20 Top view 85 25 80 30 75 35 40 45 50 55 60 65 70 P67/A23 P66/A22 P65/A21 P64/A20 DVCC3 P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 A54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/A7 P46/A6 P45/A5 P44/A4 P43/A3 P42/A2 P41/A1 P40/A0 P37/D31 P36/D30 DVSS3 P35/D29 P34/D28 P33/D27 P32/D26 P31/D25 P30/D24 P27/D23 P26/D22 Figure 2.1.1 Pin Assignment Diagram (144-pin QFP) PC3/INT0 DVSS2 DVCC2 P00/D0 P01/D1 P02/D2 P03/D3 P04/D4 P05/D5 P06/D6 P07/D7 P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 RTCVCC XT1 XT2 DVCC1 X1 DVSS1 X2 AM0 AM1 RESET BE 92C820-5 2007-02-16 TMP92C820 2.2 PAD Layout Table 2.2.1 PAD Layout (144-pin chip) Unit: m Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name DVSS2 DVCC2 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 DVSS3 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 P53 P54 X Point -440 -340 -240 -140 -40 59 160 260 360 460 561 661 761 861 961 1062 1162 1263 1363 1474 1589 1702 1814 1926 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 Y Point -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -1924 -1799 -1674 -1548 -1426 -1311 -1199 -1087 -975 -864 -757 -648 -541 -435 -332 -228 -128 -28 71 171 272 374 477 581 Pin No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name P55 P56 P57 P60 P61 P62 P63 DVCC3 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P80 DVSS4 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PA0 PA1 PA2 AVSS AVCC X Point 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 1925 1800 1675 1558 1448 1346 1243 1141 1038 937 835 734 633 532 431 330 229 128 28 -72 -173 -274 -375 -477 -580 -684 -788 -892 -996 -1101 -1208 -1319 -1430 -1555 -1828 -1955 Y Point 685 789 894 1000 1107 1213 1321 1430 1546 1672 1798 1924 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 2211 (Chip size 4.68 mm x 4.68 mm) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name VREFL VREFH PG0 PG1 PG2 PG3 PG4 PA3 PA4 PA5 PA6 PA7 PC0 PC1 PC5 PC6 PF0 PF1 PF2 PF3 PF4 PF5 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PK0 PK1 PK2 PK3 PK4 PK6 RTCVCC XT1 XT2 BE X Point -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -1962 -1851 -1574 -1466 -1360 -1257 -1057 -957 -840 -740 -640 -540 Y Point 1945 1820 1694 1568 1460 1353 1249 1050 946 842 739 635 531 427 326 224 123 23 -77 -179 -284 -388 -493 -598 -704 -809 -914 -1024 -1132 -1243 -1354 -1464 -1576 -1701 -1826 -1953 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 -2213 DVCC1 X1 DVSS1 X2 AM0 AM1 RESET PC3 92C820-6 2007-02-16 TMP92C820 2.3 Pin Names and Functions The following table shows the names and functions of the input/output pins. Table 2.3.1 Pin Names and Functions (1/3) Pin Names D0 to D7 P10 to P17 D8 to D15 P20 to P27 D16 to D23 P30 to P37 D24 to D31 P40 to P47 A0 to A7 P50 to P57 A8 to A15 P60 to P67 A16 to A23 P70 RD Number of Pins 8 8 8 8 8 8 8 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O Output I/O Output I/O Output Output Output Output Output Output Output Output Output Output Output Output Output I/O Input Output Functions Data: Data bus 0 to 7. Port 1: I/O port. Input or output specifiable in units of bits. Data: Data bus 8 to 15. Port 2: I/O port. Input or output specifiable in units of bits. Data: Data bus 16 to 23. Port 3: I/O port. Input or output specifiable in units of bits. Data: Data bus 24 to 31. Port 4: I/O port. Input or output specifiable in units of bits. Address: Address bus 0 to 7. Port 5: I/O port. Input or output specifiable in units of bits. Address: Address bus 8 to 15. Port 6: I/O port. Input or output specifiable in units of bits. Address: Address bus 16 to 23. Port 70: Output port Read: Outputs strobe signal to read external memory. Port 71: Output port Write: Output strobe signal for writing data on pins D0 to D7. Port 72: Output port Write: Output strobe signal for writing data on pins D8 to D15. Port 73: Output port Write: Output strobe signal for writing data on pins D16 to D23. Port 74: Output port Write: Output strobe signal for writing data on pins D24 to D31. Port 75: Output port Read/Write: 1 represents read or dummy cycle; 0 represents write cycle. Port 76: I/O port Wait: Signal used to request CPU bus wait. Port 80: Output port Chip select 0: Outputs "low" when address is within specified address area. Chip select for SDRAM: Outputs "0" when address is within SDRAM upper-address area. Port 81: Output port Chip select 1: Outputs "low" when address is within specified address area. Chip select for SDRAM: Outputs "0" when address is within SDRAM lower-address area. Port 82: Output port Chip select 2: Outputs "low" when address is within specified address area. Expand chip select 2A: Outputs "0" when address is within specified address area. Port 83: Output port Chip select 3: Outputs "low" when address is within specified address area. Port 84: Output port Chip select 24: Outputs "0" when address is within specified address area. Expand chip select 2B: Outputs "0" when address is within specified address area. Port 85: Output port Chip select 25: Outputs "0" when address is within specified address area. Expand chip select 2C: Outputs "0" when address is within specified address area. Port 86: Output port Expand chip select 2D: Outputs "0" when address is within specified address area. Port 87: Output port Clock for SDRAM P71 WRLL P72 WRLU P73 WRUL P74 WRUU P75 R/ W P76 WAIT P80 CS0 SDCSH 1 Output Output Output P81 CS1 SDCSL 1 Output Output Output P82 CS2 CS2A 1 Output Output Output Output Output Output Output Output P83 CS3 1 P84 EA24 CS2B 1 P85 EA25 CS2C 1 Output Output Output Output Output Output P86 CS2D 1 1 P87 SDCLK 92C820-7 2007-02-16 TMP92C820 Table 2.3.1 Pin Names and Functions (2/3) Pin Names P90 SCK P91 SO SDA P92 SI SCL P93 CS2E Number of Pins 1 I/O I/O I/O I/O Output I/O I/O Port 90: I/O port Functions Serial bus interface clock I/O data at SIO mode. Port 91: I/O port Serial bus interface send data at SIO mode. Serial bus interface send/receive data at I C mode. (Open drain/output mode by programmable.) Port 92: I/O port Serial bus interface receive data at SIO mode. Serial bus interface clock I/O data at I C mode. (Open drain/output mode by programmable.) Port 93: I/O port Expand chip select 2E: Outputs "0" when address is within specified address area. Port 94: I/O port Expand chip select 2F: Outputs "0" when address is within specified address area. Port 95: Output port Expand chip select 2G: Outputs "0" when address is within specified address area. Serial transmission data 2. Open drain/output pin by programmable. Port 96: Output port Serial receive data 2. Expand chip select EXA: Outputs "0" when address is within specified address area. A0 to A7 port: Pin used to input ports. Key input 0 to 7: Pin used of key-on wakeup 0 to 7. (Schmitt input, with pull-up resistor.) Port C0: I/O port 8-bit timer 0 input: Timer 0 input. Port C1: I/O port Interrupt request pin1 : Interrupt request pin with programmable rising /falling edge. 8-bit timer 1 output: Timer 1 output. Port C3: I/O port Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge. Port C5: I/O port Interrupt request pin 2 : Interrupt request pin with programmable rising /falling edge. 8-bit timer 3 output: Timer 3 output. Port C6: I/O port Interrupt request pin 3: Interrupt request pin with programmable rising /falling edge. Timer B0 output. Port F0: I/O port Serial 0 send data: Open drain/output pin by programmable. Port F1: I/O port Serial 0 receive data. Port F2: I/O port Serial 0 clock I/O. Serial 0 data send enable (Clear to send). Port F3: I/O port Serial 1 send data: Open drain/output pin by programmable. Port F4: I/O port Serial 1 receive data. Port F5: I/O port Serial 1 clock I/O. Serial 1 data send enable (Clear to send). Port G0 to G4 port: Pin used to input ports. Analog input 0 to 4: Pin used to Input to AD conveter. AD trigger: Signal used to request AD start (with used to PG3). 2 2 1 1 Input I/O I/O Output I/O Output I/O Output Output I/O 1 1 P94 CS2F P95 CS2G 1 TXD2 P96 RXD2 CSEXA 1 Input Output Input PA0 to PA7 KI0 to KI7 PC0 TA0IN PC1 INT1 TA1OUT PC3 INT0 PC5 INT2 TA3OUT PC6 INT3 TB0OUT0 PF0 TXD0 PF1 RXD0 PF2 SCLK0 CTS0 8 Input I/O Input I/O Input Output I/O Input I/O Input Output I/O 1 1 1 1 1 Input Output I/O Output I/O Input I/O I/O Input I/O Output I/O Input I/O I/O Input Input 1 1 1 PF3 TXD1 PF4 RXD1 PF5 SCLK1 CTS1 1 1 1 PG0 to PG4 AN0 to AN4 ADTRG 5 Input Input 92C820-8 2007-02-16 TMP92C820 Table 2.3.1 Pin Names and Functions (3/3) Pin Names PJ0 SDRAS Number of Pins 1 I/O Output Output Output Output Output Port J0: Output port Functions Row address strobe for SDRAM: Outputs "0" when address is within SDRAM address area. Port J1: Output port Column address strobe for SDRAM: Outputs "0" when address is within SDRAM address area. Port J2: Output port Write enable for SDRAM. Write for SRAM: Strobe signal for writing data . Port J3: Output port Data enable for SDRAM on pins D0 to D7. Data enable for SRAM on pins D0 to D7. Port J4: Output port Data enable for SDRAM on pins D8 to D15. Data enable for SRAM on pins D8 to D15. Port J5: Output port Data enable for SDRAM on pins D16 to D23. Data enable for SRAM on pins D16 to D23. Port J6: Output port Data enable for SDRAM on pins D24 to D32. Data enable for SRAM on pins D24 to D32. Port J7: Output port Clock enable for SDRAM. Port K0: Output port LCD driver output pin. Port K1: Output port LCD driver output pin. Port K2: Output port LCD driver output pin. Port K3: Output port LCD driver output pin. Port K4: Output port LCD driver output pin. Port K6: Output port RTC alarm output pin. Melody/alarm output pin (Inverted). Port L0 to L7: I/O port Data bus for LCD driver. Backup enable. Operation mode: Fix to AM1 = "0", AM0 = "1": 16-bit external bus or 8-/16-/32-bit dynamic sizing. Fix to AM1 = "1", AM0 = "0": 32-bit external bus or 8-/16-/32-bit dynamic sizing. High-frequency oscillator connection pins. Low-frequency oscillator connection pins. Reset: Initializes TMP92C820 (with pull-up resistor). Pin for reference voltage input to AD converter (H). Pin for reference voltage input to AD converter (L). Power supply pin for AD converter. GND pin for AD converter (0 V). Power supply pins (All DVCC pins should be connected with the power supply pin). GND pins (0 V) (All DVSS pins should be connected with GND (0V)). Power supply pin for RTC and low-frequency oscillator. PJ1 SDCAS 1 PJ2 SDWE SRWR 1 Output Output Output PJ3 SDLLDQM SRLLB 1 Output Output Output PJ4 SDLUDQM SRLUB 1 Output Output Output PJ5 SDULDQM SRULB 1 Output Output Output PJ6 SDUUDQM SRUUB 1 Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output I/O Output Input Input I/O I/O Input Input Input - - - - - PJ7 SDCKE PK0 D1BSCP PK1 D2BLP PK2 D3BFR PK3 DLEBCD PK4 DOFFB PK6 ALARM MLDALM 1 1 1 1 1 1 1 PL0 to PL7 LD0 to LD7 BE 8 1 2 2 2 1 1 1 1 1 3 4 1 AM0, AM1 X1/X2 XT1/XT2 RESET VREFH VREFL AVCC AVSS DVCC DVSS RTCVCC 92C820-9 2007-02-16 TMP92C820 3. 3.1 Operation This section describes the basic components, functions and operation of the TMP92C820. CPU The TMP92C820 contains an advanced high-speed 32-bit CPU (900/H1 CPU). For CPU operation, see the TLCS-900/H1 CPU. The following describe the unique function of the CPU used in the TMP92C820; these functions are not covered in the TLCS-900/H1 CPU section. 3.1.1 CPU Outline 900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1 CPU has expanded 32-bit internal data bus to process instructions more quickly. Outline of 900/H1 CPU are as follows: Table 3.1.1 CPU Outline 900/H1 CPU Width of CPU address bus Width of CPU data bus Internal operating frequency Minimum bus cycle Data bus sizing Internal RAM Internal I/O External device Minimum instruction Execution cycle Conditional jump Instruction queue buffer Instruction set CPU mode Micro DMA 2 clocks (100 ns at 20 MHz) 12 bytes Compatible with TLCS-900, 900/L, 900/H, 900/L1 and 900/H2 (NORMAL, MAX, MIN and LDX instruction is deleted.) Only maximum mode 8 channels 24 bits 32 bits 20 MHz 1-clock access (50 ns at 20 MHz) 8/16/32 bits 32 bits 1-clock access 8-/16-bit 8-/16-bit 8 bits 2-clock access (can insert some waits.) 1 clock (50 ns at 20 MHz) 2-clock access 5 to 6-clock access 900/H1 I/O 900/L1 I/O 92C820-10 2007-02-16 TMP92C820 3.1.2 Reset Operation When resetting the TMP92C820 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input low for at least 20 system clocks (16 s at 40 MHz). When the reset has been accepted, the CPU performs the following: * Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<7:0> PC<15:8> * * * Data in location FFFF00H Data in location FFFF01H PC<23:16> Data in location FFFF02H Sets the stack pointer (XSP) to 00000000H. Sets bits When the reset is released, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. * * Initializes the internal I/O registers as table of "Table of Special Function Registers (SFRs)" in section 5. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Internal RESET is released as soon as external reset is released. The operation of memory controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on the TMP92C820 may be spoiled because the control signals are unstable until power supply becomes stable after power on reset. 92C820-11 2007-02-16 TMP92C820 VCC 3.3 V RESET 10 ms (Min) Osc warm-up time + 20 system clock 0 s (Min) Figure 3.1.1 Power on Reset Timing Example 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins to "10" to use 32-bit external bus, or set it to "01" to use 16-bit external bus. Table 3.1.2 Operation Mode Setup Table Operation Mode 16-bit external bus or 8-/16-/32-bit dynamic bus sizing 32-bit external bus or 8-/16-/32-bit dynamic bus sizing Mode Setup Input Pin RESET AM1 0 AM0 1 1 0 92C820-12 2007-02-16 TMP92C820 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92C820. 1H 000000H Internal I/O (8 Kbytes) 000100H 001FE0H 002000H Internal RAM (8 Kbytes) 004000H Direct area (n) 64-Kbyte area (nn) 010000H External memory F00000H Provisional emulator control area (64 Kbytes) F10000H 16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) (Note 1) External memory FFFF00H FFFFFFH Vector table (256 bytes) (Note 2) ( = Internal area) Note 1: Provisional emulator control area is for emulator, it is mapped F00000H to F10000H address after reset. Note 2: Don't use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved. Note 3: On emulator WR signal and RD signal are asserted, when provisional emulator control area is accessed. Be careful to use external memory. Figure 3.2.1 Memory Map 92C820-13 2007-02-16 TMP92C820 3.3 Clock Function and Standby Function TMP92C820 contains (1) Clock gear, (2) Standby controller, and (3) Noise reduction circuit. It is used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 2H 3H 4H 5H 6H 7H 8H 9H 10H 1H Block Diagram of System Clock SFR System Clock Controller Noise Reduction Circuits Standby Controller 92C820-14 2007-02-16 TMP92C820 The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only) and (b) Dual clock mode (X1, X2, XT1, and XT2 pins). Figure 3.3.1 shows a transition figure. 12H Reset (fOSCH/32) IDLE2 mode (I/O operate) Instruction Interrupt Instruction Release reset NORMAL mode (fOSCH/gear value/2) IDLE1 mode Interrupt (Operate only oscillator) (a) Instruction STOP mode Interrupt (Stops all circuits) Single clock mode transition figure Reset (fOSCH/32) IDLE2 mode (I/O operate) Instruction Interrupt Instruction Release reset NORMAL mode Instruction IDLE1 mode Interrupt (Operate only oscillator) IDLE2 mode (I/O operate) (fOSCH/gear value/2) Instruction SLOW mode (fs/2) Interrupt STOP mode (Stops all circuits) Instruction Interrupt Instruction IDLE1 mode Interrupt (Operate only oscillator) (b) Instruction Dual clock mode transition figure Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 92C820-15 2007-02-16 TMP92C820 3.3.1 Block Diagram of System Clock SYSCR0 Low-frequency oscillator T T0 /4 /8 fs fs fc /2 fc/2 fc/4 fc/8 fc/16 /2 /4 /8 /16 fSYS /2 fio SYSCR0 High-frequency oscillator SYSCR1 fOSCH SYSCR1 Clock gear fSYS fio T0 TMRA0 to TMRA3, TMRB0 Prescaler CPU RAM Interrupt controller SIO0 to SIO2 Prescaler ADC I/O ports SBI T Prescaler SDRAMC LCDC RTC fs MLD/ALM WDT Figure 3.3.2 Block Diagram of System Clock 92C820-16 2007-02-16 TMP92C820 3.3.2 SFR 7 SYSCR0 Bit symbol (10E0H) Read/Write After reset Function XEN R/W 1 High-frequency oscillator (fc) 0: Stop 1: Oscillation 6 XTEN 1 Low-frequency oscillator (fs) 0: Stop 1: Oscillation 5 4 3 2 WUEF R/W 0 Warm-up timer 0: Write Don't care 1: Write start timer 0: Read end warm up 1: Read do not end warm up 1 0 SYSCR1 Bit symbol (10E1H) Read/Write After reset Function SYSCK 0 Select system clock. 0: fc 1: fs GEAR2 R/W 1 GEAR1 0 GEAR0 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: 110: Reserved 111: HALTM0 R/W 1 SELDRV 0 SYSCR2 Bit symbol (10E2H) Read/Write After reset Function - R/W 0 Always write "0". WUPTM1 1 WUPTM0 0 HALTM1 1 Warm-up timer 00: Reserved 8 01: 2 /inputted frequency 14 10: 2 /inputted frequency 16 11: 2 /inputted frequency HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode Note 1: The unassigned register, SYSCR0 Note 2: By reset, low-frequency oscillator is enabled. Figure 3.3.3 SFR for System Clock 92C820-17 2007-02-16 TMP92C820 7 EMCCR0 Bit symbol (10E3H) Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON 6 5 4 3 2 EXTIN 0 1 DRVOSCH R/W 1 0 DRVOSCL 1 fs oscillator drive ability 1: Normal 0: Weak 1: fc external fc oscillator clock drive ability 1: Normal 0: Weak EMCCR1 Bit symbol (10E4H) Read/Write EMCCR2 After reset (10E5H) Function Switching the protect ON/OFF by write to following 1st-key, 2nd-key 1st-Key: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-Key: EMCCR1 = A5H, EMCCR2 = 5AH in succession write Figure 3.3.4 SFR for Noise-reduction Note: In caseWhen restarting the oscillator in from the stop oscillation state (e.g. Restart restarting the oscillator in STOP mode), set EMCCR0 92C820-18 2007-02-16 TMP92C820 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 13H Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.1 Warm-up Times Warm-up Time SYSCR2 01 (2 /frequency) 10 (2 /frequency) 11 (2 /frequency) 16 14 8 Change to NORMAL Mode (fc) 6.4 [s] 409.6 [s] 1.638 [ms] Change to SLOW Mode (fs) 7.8 [ms] 500 [ms] 2000 [ms] at fOSCH = 40 MHz, fs = 32.768 kHz 92C820-19 2007-02-16 TMP92C820 Example 1: Setting the clock Changing from high frequency (fc) to low frequency (fs). EQU 10E0H EQU 10E1H EQU 10E2H LD (SYSCR2), 0X11 - - - - B SET 6, (SYSCR0) SET 2, (SYSCR0) WUP: BIT 2, (SYSCR0) JR NZ, WUP SET 3, (SYSCR1) RES 7, (SYSCR0) X: Don't care, -: No change SYSCR0 SYSCR1 SYSCR2 ; ; ; ; ; ; ; Sets warm-up time to 2 /fs. Enables low-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fc to fs. Disables high-frequency oscillation. 16 Counts up by fSYS Counts up by fs 92C820-20 2007-02-16 TMP92C820 Example 2: Setting the clock Changing from low frequency (fs) to high frequency (fc). EQU 10E0H EQU 10E1H EQU 10E2H LD (SYSCR2), 0X10 - - - - B SET 7, (SYSCR0) SET 2, (SYSCR0) WUP: BIT 2, (SYSCR0) JR NZ, WUP RES 3, (SYSCR1) RES 6, (SYSCR0) X: Don't care, -: No change SYSCR0 SYSCR1 SYSCR2 ; ; ; ; ; ; ; Sets warm-up time to 2 /fc. Enables high-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fs to fc. Disables low-frequency oscillation. 14 Counts up by fSYS Counts up by fc 92C820-21 2007-02-16 TMP92C820 (2) Clock gear controller fFPH is set according to the contents of the clock gear select register SYSCR1 SYSCR1 X: Don't care EQU LD 10E1H (SYSCR1), XXXX0000B ; Changes fSYS to fc/2. (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 (Example) SYSCR1 EQU LD LD 10E1H (SYSCR1), XXXX0001B ; (DUMMY), 00H ; Instruction to be executed after clock gear has changed Changes fSYS to fc/4. Dummy instruction 92C820-22 2007-02-16 TMP92C820 3.3.4 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) Runaway provision with SFR protection register (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH Enable oscillation (STOP + EMCCR0 X1 pin C1 Resonator C2 X2 pin (Setting method) The drivability of the oscillator is reduced by writing "0" to EMCCR0 92C820-23 2007-02-16 TMP92C820 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Enable oscillation Resonator EMCCR0 C2 (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0 (3) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation (STOP + EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing "1" to EMCCR0 92C820-24 2007-02-16 TMP92C820 (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (Memory controller, MMU) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR MMU LOCAL 0/1/2/3 Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 2. 3. (Operation explanation) Execute and release of protection (Write operation to specified SFR) become possible by setting up a double key to EMCCR1 and EMCCR2 register. (Double key) 1st-key: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd-key: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2 A state of protection can be confirmed by reading EMCCR0 92C820-25 2007-02-16 TMP92C820 3.3.5 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 14H Table 3.3.2 SFR Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRB0 SIO0 SIO1 AD converter WDT SBI SFR TA01RUN 2. 3. IDLE1: Only the oscillator, the RTC (Real time clock) and MLD (Melody-alarm generator) continue to operate. STOP: All internal circuits stop operating. 15H The operation of each of the different HALT modes is described in Table 3.3.3. Table 3.3.3 I/O Operation during HALT Modes HALT Modes SYSCR2 CPU I/O ports TMRA, TMRB Block SIO, SBI (Note) AD converter WDT LCDC, SDRAMC interrupt controller RTC, MLD Operate Operate Keep the state when the HALT instruction was executed. Available to select operation block (Note) Stop IDLE2 11 Stop 16H IDLE1 10 17H STOP 01 See Table 3.3.6, Table 3.3.7 and Table 3.3.8 18H Note: Prohibited in the synchronous mode of SBI circuit. 92C820-26 2007-02-16 TMP92C820 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register 19H 1. Released by requesting an interrupt The operating released from the HALT mode depends on the interrupt enabled status. When the interrupt request level set before executing the HALT instruction exceeds the value of interrupt mask register, the interrupt due to the source is processed after releasing the HALT mode, and CPU status executing an instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is not executed. (In non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 to INT3, INTKEY, INTRTC, and INTALM0 to INTALM4 interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is executed. In this case, interrupt processing, and CPU starts executing the instruction next to the HALT instruction, but the interrupt request flag is held at "1". Note: Usually, interrupts can release all halts status. However, the interrupts (INT0 to INT3, INTKEY, INTRTC, INTALM0 to INTALM4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. 2. Releasing by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by RESET, it is necessary enough resetting time (See Table 3.3.5) to set the operation of the oscillator to be stable. 20H When releasing the HALT mode by resetting, the internal RAM data keeps the state before the "HALT" instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the "HALT" instruction is executed.) 92C820-27 2007-02-16 TMP92C820 Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode INTWDT Source of Halt State Clearance Interrupt Enabled (Interrupt level) (Interrupt mask) IDLE2 Initialize LSI Interrupt Disabled (Interrupt level) < (Interrupt mask) IDLE2 - IDLE1 x x x x x x x STOP x *1 x x x x x *1 x x x IDLE1 - STOP - INT0 to 3 (Note1) INTALM0 to 4 INTTA0 to 3, INTTB00 to 01 Interrupt x x x x x x x x *1 x x x x x INTRX0 to 2, TX0 to 2 INTSS0 to 2 INTAD INTKEY INTRTC INTSBE0 INTLCD RESET x x x x *1 x x x : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. x: It can not be used to release the HALT mode. -: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. (Example releasing IDLE1 mode) An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH INT0 LD LD LD EI LD HALT (PCFC), 04H (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; ; ; ; ; ; Sets PC3F to INT0. Selects INT0 interrupt rising edge. Sets INT0 interrupt level to 6. Sets interrupt level to 5 for CPU. Sets HALT mode to IDLE1 mode. Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 92C820-28 2007-02-16 TMP92C820 (3) Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.5 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. 21H X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt of releasing halt IDLE2 mode Figure 3.3.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC and MLD continue to operate. The system clock in the MCU stops. The pin status in the IDLE1 mode is depended on setting the register SYSCR2 2H 0H23 24H In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.6 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. 25H X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt of releasing halt IDLE1 mode Figure 3.3.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 92C820-29 2007-02-16 TMP92C820 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 26H 27H 28H After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.7 illustrates the timing for clearance of the STOP mode halt state by an interrupt. 29H Warm-up time X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt of releasing halt STOP mode Figure 3.3.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.5 Sample Warm-up Times after Clearance of STOP Mode at fOSCH = 40 MHz, fs = 32.768 kHz SYSCR0 0 (fc) SYSCR2 6.4 s 8 10 (214) 409.6 s 11 (216) 1.638 ms 92C820-30 2007-02-16 TMP92C820 Table 3.3.6 Input Buffer State Table Input Buffer State Port Name Input Function Name When the CPU is operating During Reset When used as function pin In HALT mode (IDLE2) When used as Input pin - In HALT mode (IDLE1/STOP) Condition A (Note) When used as Function pin When used as Input pin - Condition B (Note) When used as Function pin When used as Input pin - When used When used as as Function Input pin pin - D0-D7 P10-P17 P20-P27 D0-D7 D8-D15 D16-D23 OFF ON upon external read 16-bit start :ON 32-bit start :OFF ON upon external read of LCDC OFF OFF P30-P37 P40-P47 P50-P57 P60-P67 P76 P90 P91 P92 P93 P94 P95 P96 PA0-PA7 (*1) PC0 PC1 PC3 PC5 PC6 PF0 PF1 PF2 PF3 PF4 PF5 PG0-PG2, PG4 (*2) PG3 (*2) PL0-PL7 BE D24-D31 - - - OFF - - OFF - - OFF OFF WAIT SCK SDA SI, SCL - - - - OFF ON ON OFF OFF ON - - - RXD2 KI0-7 TA0IN INT1 INT0 INT2 INT3 - - - ON ON OFF ON OFF OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON ON ON ON ON - - RXD0 SCLK0, CTS0 - ON - ON - ON OFF ON OFF - OFF OFF - OFF RXD1 SCLK1, CTS1 - ON - ON ON upon port read ON - OFF - OFF - OFF ADTRG - - - - ON - ON - OFF ON - ON - - RESET (*1) AM0, AM1 X1, XT1 ON ON - ON - ON ON - IDLE1 : ON , STOP : OFF ON: The buffer is always turned on. A current flows the *1: Port having a pull-up/pull-down resistor. input buffer if the input pin is not driven. OFF: The buffer is always turned off. -: No applicable *2: AIN input does not cause a current to flow through the buffer. Note: Condition A/B are as follows. SYSCR2 register setting HALT mode 92C820-31 2007-02-16 TMP92C820 Table 3.3.7 Output Buffer State Table (1/2) Output Buffer State Port Name Output Function Name When the CPU is Operating When used When Used as as Function Output Port Pin - In HALT mode (IDLE2) When Used as Function Pin When Used as Output Port - During Reset In HALT mode (IDLE1/STOP) Condition A (Note) Condition B (Note) When Used When Used When Used When Used as as as as Function Output Port Function Pin Output Port Pin - - D0-D7 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70 P71 P72 P73 P74 P75 P76 P80 D0-D7 D8-D15 D16-D23 D24-D31 A0-A7 A8-A15 A16-A23 RD WRLL WRLU WRUL WRUU R/W - - ON upon OFF external write OFF ON OFF OFF ON ON ON ON OFF - - - CS0, SDCSH CS1, SDCSL CS2, CS2A CS3 EA24, CS2B EA25, CS2C CS2D SDCLK SCK SO SCL CS2E CS2F CS2G TXD2 CSEXA - - - - - P81 P82 P83 P84 ON ON ON OFF ON P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 PC0 PC1 PC3 PC5 PC6 ON ON OFF ON OFF TA1OUT - ON - ON - OFF - ON - TA3OUT TB0OUT ON ON OFF ON 92C820-32 2007-02-16 TMP92C820 Table 3.3.8 Output Buffer State Table (2/2) Output Buffer State When the CPU is Operating During Reset When used as Function Pin PF0 PF1 PF2 PF3 PF4 PF5 PJ0 PJ1 PJ2 TXD0 - Port Name Output Function Name In HALT mode (IDLE2) When Used as Function Pin ON - In HALT mode (IDLE1/STOP) Condition A (Note) Condition B (Note) When Used as Function Pin When Used as Output Port When Used as Output Port When Used as Output Port When Used as Function Pin OFF - When Used as Output Port ON - - SCLK0 TXD1 - ON - ON - OFF - ON - SCLK1 SDRAS SDCAS SDWE SRWR SDLLDQM SRLLB SDLUDQM SRLUB SDULDQM SRULB SDUUDQM SRUUB SDCKE D1BSCP D2BLP D3BFR DLEBCD DOFFB ALARM MLDALM LD0-LD7 - - PJ3 OFF PJ4 OFF ON ON OFF ON PJ5 PJ6 ON ON ON ON in self refresh cycle PJ7 PK0 PK1 PK2 PK3 PK4 PK6 PL0-PL7 X2 XT2 OFF ON - - IDLE1: ON, STOP: output "H" level IDLE1: ON, STOP: High-Z ON: The buffer is always turned on. When the bus is released, however, output buffers for some pins are turned off. OFF: The buffer is always turned off. -: No applicable *1: Port having a pull-up/pull-down resistor. Note: Condition A/B are as follos. SYSCR2 register setting HALT mode IDLE1 STOP Condition B Condition A Condition A Condition B Condition B 92C820-33 2007-02-16 TMP92C820 3.4 Interrupts Interrupts are controlled by the CPU interrupt mask register 0H 92C820-34 2007-02-16 TMP92C820 Interrupt processing Micro DMA soft start request Interrupt specified by micro DMA start vector? No Yes Clear interrupt request flag Interrupt vector value "V" read Interrupt request F/F clear General-purpose interrupt processing Data transfer by micro DMA PUSH PC PUSH SR SR Count Count - 1 Micro DMA processing Count = 0 Yes Clear vector register generating micro DMA transfer end interrupt (INTTC0 to INTTC7) PC (FFFF00H + V) No Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 92C820-35 2007-02-16 TMP92C820 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4), and (5). (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level has been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: The smaller the vector value, the higher the priority.) (2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (Pointed to by XSP). (3) The CPU sets the value of the CPU's interrupt mask register 1H 92C820-36 2007-02-16 TMP92C820 Table 3.4.1 TMP92C820 Interrupt Vectors and Micro DMA Start Vectors (1/2) Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Maskable Non maskable Type Interrupt Source and Source of Micro DMA Request Reset or [SWI0] instruction [SWI1] instruction Illegal instruction or [SWI2] instruction [SWI3] instruction [SWI4] instruction [SWI5] instruction [SWI6] instruction [SWI7] instruction (Reserved) INTWD: Watchdog timer Micro DMA INT0: INT0 pin input INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input (Reserved) INTALM0: ALM0 (8 kHz) INTALM1: ALM1 (512 Hz) INTALM2: ALM2 (64 Hz) INTALM3: ALM3 (2 Hz) INTALM4: ALM4 (1 Hz) INTP0: Protect 0 (WR to SFR) (Reserved) INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTB0: 16-bit timer 0 INTTB1: 16-bit timer 0 INTKEY: Key wakeup INTRTC: RTC (Alarm interrupt) INTTBO0: 16-bit timer 0 (Overflow) INTLCD: LCDC/LP pin INTRX0: Serial receive (Channel 0) INTTX0: Serial transmission (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial transmission (Channel 1) INTRX2: Serial receive (Channel 2) INTTX2: Serial transmission (Channel 2) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) INTSBE0: SBI I C bus transfer end (Channel 0) (Reserved) (Reserved) 2 Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H Address Refer to Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H Micro DMA Start Vector - (Note 1) 0AH (Note 2) 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H (Note 2) 21H 22H (Note 2) 23H 24H (Note 2) 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 92C820-37 2007-02-16 TMP92C820 Table 3.4.1 TMP92C820 Interrupt Vectors and Micro DMA Start Vectors (2/2) Default Priority 51 52 53 54 55 56 57 58 59 60 - to - (Reserved) Maskable Type Interrupt Source and Source of Micro DMA Request (Reserved) INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) INTTC4: Micro DMA end (Channel 4) INTTC5: Micro DMA end (Channel 5) INTTC6: Micro DMA end (Channel 6) INTTC7: Micro DMA end (Channel 7) Vector Value 00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H 00E4H 00E8H 00ECH 00F0H : 00FCH Address Refer to Vector FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H FFFFE4H FFFFE8H FFFFECH FFFFF0H : FFFFFCH Micro DMA Start Vector 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH - - Note 1: Micro DMA default priority. Micro DMA initiation takes priority over other maskable interrupt. Note 2: When initiating micro DMA, set at edge detect mode. 92C820-38 2007-02-16 TMP92C820 3.4.2 Micro DMA processing In addition to general-purpose interrupt processing, the TMP92C820 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source. Because the micro DMA function is implemented though the CPU, when the CPU is placed in a state of standby by HALT instruction, the requirements of the micro DMA will be ignored (Pending). Micro DMA supports 8 channels and can be transferred continuously by specifying the micro DMA burst function as below. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The eight micro DMA channels allow micro DMA processing to be set for up to 8 types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte, two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: The lower the channel number, the higher the priority (Channel 0 thus has the highest priority and channel 7 the lowest). If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general-purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (j.e, interrupt requests should be disabled). If micro DMA and general-purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. (Note) In this case, edge-triggered interrupts are the only kinds of general interrupts which can be accepted. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 2H 92C820-39 2007-02-16 TMP92C820 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: One-byte transfer, two-byte (One word) transfers and four-byte transfers. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.4.2 (4) "Detailed description of the transfer mode register". Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (Provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 34 different interrupts - the 33 interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer destination address INC mode (Micro DMA transfers are the same in every mode except counter mode). (The conditions for this cycle are as follows: external 8-bit bus, 0 waits, and even-numbered transfer source and transfer destination addresses). 3H 4H One state 1 CLK 2 3 4 5 A0 to A23 src dst Note: In fact, src and dst address are not output to A23 to A0 pins because they are internal RAM address States 1 and 2: Instruction fetch cycle (Prefetches the next instruction code) If the instruction queue buffer is FULL, this cycle becomes a dummy cycle. State 3: Micro DMA read cycle. State 4: Micro DMA write cycle. State 5: (The same as in state 1, 2.) Figure 3.4.2 Timing for Micro DMA Cycle 92C820-40 2007-02-16 TMP92C820 (2) Soft start function The TMP92C820 can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a Write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once. (If write "0" to each bit, micro DMA doesn't operate). On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. Only one channel can be set for DMA request at once. (Do not write "1" to plural bits.) When writing again 1 to the DMAR register, check whether the bit is "0" before writing "1". If read "1", micro DMA transfer isn't started yet. When a burst is specified by the DMAB register, data is transferred continuously from the initiation of micro DMA until the value in the micro DMA transfer counter is 0. If execatee soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writign to other bits by mistake. Symbol Name DMA request Address 109H (Prohibit RMW) 7 DREQ7 0 6 DREQ6 0 5 DREQ5 0 4 DREQ4 0 R/W 3 DREQ3 0 2 DREQ2 0 1 DREQ1 0 0 DREQ0 0 DMAR 1: DMA request in software (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form LDC cr,r can be used to set these registers. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0: Using only lower 24 bits. DMA destination address register 0: Using only lower 24 bits. DMA counter register 0: 1 to 65536. DMA mode register 0. Channel 7 DMAS7 DMAD7 DMAC7 DMAM7 DMA source address register 7. DMA destination address register 7. DMA counter register 7. DMA mode register 7. 8 bits 16 bits 32 bits 92C820-41 2007-02-16 TMP92C820 (4) Detailed description of the transfer mode register 0 0 0 Mode DMAM0 to DMAM7 DMAM [4:0] 000ZZ Mode Description Destination INC mode (DMADn+) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTCn Destination DEC mode (DMADn-) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source INC mode (DMADn) (DMASn+) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source DEC mode (DMADn) (DMASn-) DMACn DMACn - 1 if DMACn = 0 then INTTCn Execution Time 5 states 001ZZ 5 states 010ZZ 5 states 011ZZ 5 states 100ZZ Source and destination INC mode (DMADn+) (DMASn+) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source and destination DEC mode (DMADn-) (DMASn-) DMACn DMACn - 1 If DMACn = 0 then INTTCn Destination and fixed mode (DMADn) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTCn Counter mode DMASn DMASn + 1 DMACn DMACn - 1 if DMACn = 0 then INTTCn 6 states 101ZZ 6 states 110ZZ 5 states 11100 5 states ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = Reserved Note 1: The execution time is measured at 1 states = 50 ns (Operation at internal 20 MHz). Note 2: n stands for the micro DMA channel number (0 to 7). DMADn+/DMASn+: Post increment (Register value is incremented after transfer). DMADn-/DMASn-: Post decrement (Register value is decremented after transfer). "I/O" signifies fixed memory addresses; "memory" signifies incremented or decremented memory addresses. Note2: The transfer mode register should not be set to any value other than those listed above. 92C820-42 2007-02-16 TMP92C820 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 52 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when a reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing a micro DMA start vector to the INTCLR register). 5H An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). Six interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupt (Watchdog timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt's vector address to the CPU. The CPU compares the mask value set in 6H 7H 92C820-43 2007-02-16 Interrupt controller Interrupt request F/F S Q 1 Interrupt request signal to CPU RESET Priority encoder 1 3 INTRQ2 to 0 3 3 if INTRQ2 to 0 IFF 2 to 0 then 1. CPU (Reserved) R IFF2:0 EI1 to 7 DI Interrupt level detect Interrupt mask F/F RESET interrupt vector read INTWD Priority setting register 7 6 D Q CLR Interrupt request F/F S Q Dn + 3 D0 D1 36 D2 D3 Interrupt vector generator D4 D5 D6 R 1 2 Highest priority A 3 interrupt B 4 level selectC 5 6 7 Dn Dn + 1 Dn + 2 V = 20H V = 24H Decoder Y1 A Y2 Y3 B Y4 Y5 C Y6 6 Interrupt request signal INT0 Reset INT1 INT2 INT3 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 INTTA0 Interrupt request F/F Interrupt vector read Micro DMA acknowledge V = 28H V = 2CH V = 30H V = 34H V = 3CH V = 40H V = 44H V = 48H V = 4CH V = 58H During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller D7 V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH Soft start 34 D 6 CLR INTTC0 DMA0V DMA1V DMA2V DMA3V Q S Selector 2 4 Interrupt vector read 4-input OR 0 A 1 2 B 3 Micro DMA channel priority encoder 92C820-44 Halt release RESET INT0, 1, 2, 3, INTKEY, INTRTC, INTALM Micro DMA counter 0 interrupt INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 Micro DMA start vector setting register if IFF = 7 then 0 Micro DMA request D5 D4 D3 D2 D1 D0 2 Micro DMA channel specification TMP92C820 2007-02-16 RESET TMP92C820 (1) Interrupt priority setting registers Symbol Name INT0& INTAD enable Address 7 IADC R 0 6 INTAD IADM2 0 INT2 I2M2 0 - - 5 IADM1 R/W 0 I2M1 R/W 0 - - 4 IADM0 0 I2M0 0 - 3 I0C R 0 I1C R 0 I3C R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 ITA0M2 0 ITA2M2 0 ITB0M2 0 INTTBO0 ITBO0M2 0 INTRX0 IRX0M2 0 INTRX1 IRX1M2 0 INTSBE0 ISBE0M2 0 INTALM0 IA0M2 0 INTALM2 IA2M2 0 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITB0M1 R/W 0 ITBO0M1 R/W 0 IRX0M1 R/W 0 IRX1M1 R/W 0 ISBE0M1 R/W 0 IA0M1 R/W 0 IA2M1 R/W 0 0 I0M0 0 I1M0 0 I3M0 0 ITA0M0 0 ITA2M0 0 ITB0M0 0 ITBO0M0 0 IRX0M0 0 IRX1M0 0 ISBE0M0 0 IA0M0 0 IA2M0 0 INTE0AD F0H INTE12 INT1&INT2 enable D0H I2C R 0 INTE3 INT3 enable D1H - - Always write "0". INTTA1 (TMRA1) INTTA0& INTETA01 INTTA1 enable D4H ITA1C R 0 INTTA2& INTETA23 INTTA3 enable ITA3C R 0 INTTB0& INTETB01 INTTB1 enable ITB1C R 0 INTTBO0 (Overflow) enable - R 0 INTRX0& INTTX0 enable ITX0C R 0 INTRX1& INTTX1 enable ITX1C R 0 INTSBE0 enable - - INTALM1 INTALM0& INTEALM 01 INTALM1 INTTA0 (TMRA0) ITA1M0 0 ITA3M0 0 ITB1M0 0 - 0 ITX0M0 0 ITX1M0 0 - ITA0C R 0 ITA2C R 0 ITB0C R 0 ITBO0C R 0 IRX0C R 0 IRX1C R 0 ISBE0C R 0 IA1M0 0 IA3M0 0 IA0C R 0 IA2C R 0 ITA1M2 0 ITA3M2 0 ITB1M2 0 - - 0 ITA1M1 R/W 0 ITA3M1 R/W 0 ITB1M1 R/W 0 - R/W 0 INTAT3 (TMRA3) D5H INTAT2 (TMRA2) INTTB1 (TMRB1) D8H INTTB0 (TMRB0) INTETBO0 DAH INTTX0 INTES0 DBH ITX0M2 0 INTTX1 INTES1 DCH ITX1M2 0 - INTESB0 E3H - - - Always write "0". IA1C R 0 INTALM2& INTEALM 23 INTALM3 ITX0M1 R/W 0 ITX1M1 R/W 0 E5H IA1M2 0 IA1M1 R/W 0 enable INTALM3 E6H IA3C R 0 0 IA3M2 IA3M1 R/W 0 enable 92C820-45 2007-02-16 TMP92C820 Symbol Name Address 7 - - 6 - - 5 - - 4 - 3 IA4C R 0 2 INTALM4 IA4M2 0 INTRTC IRM2 0 INTKEY IKM2 0 INTLCD ILCDM2 0 INTRX2 IRX2M2 0 INTP0 IP0M2 0 1 IA4M1 R/W 0 IRM1 R/W 0 IKM1 R/W 0 ILCDM1 R/W 0 IRX2M1 R/W 0 IP0M1 R/W 0 0 IA4M0 0 IRM0 0 IKM0 0 ILCDM0 0 IRX2M0 0 IP0M0 0 INTALM4 INTEALM4 enable E7H Always write "0". - INTRTC INTERTC enable E8H - - - INTECKEY - - - - IRC R 0 Always write "0". INTKEY enable - - - INTLCD INTLCD enable EAH - - INTTX2 INTES2 INTRX2& INTTX2 enable EDH ITX2C R 0 INTP0 enable - - 0 - INTEP0 EEH - - - Always write "0". Interrupt request flag - ITX2M2 ITX2M1 R/W 0 0 ITX2M0 - - - Always write "0". - - - - Always write "0". - E9H IKC R 0 ILCD1C R 0 IRX2C R 0 IP0C R 0 IxxM2 0 0 0 0 1 1 1 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 92C820-46 2007-02-16 TMP92C820 Symbol Name Address 7 ITC1C R 0 6 ITC1M2 0 ITC3M2 0 ITC5M2 0 ITC7M2 0 - - 5 ITC1M1 R/W 0 ITC3M1 R/W 0 ITC5M1 R/W 0 ITC7M1 R/W 0 - - 4 ITC1M0 0 ITC3M0 0 ITC5M0 0 ITC7M0 0 - 3 ITC0C R 0 ITC2C R 0 ITC4C R 0 ITC6C R 0 ITCWD R 0 2 ITC0M2 0 ITC2M2 0 ITC4M2 0 ITC6M2 0 INTWD - - 1 ITC0M1 R/W 0 ITC2M1 R/W 0 ITC4M1 R/W 0 ITC6M1 R/W 0 - - - 0 ITC0M0 0 ITC2M0 0 ITC4M0 0 ITC6M0 0 - - INTTC1 (DMA1) INTTC0& INTETC01 INTTC1 enable F1H INTTC0 (DMA0) INTTC3 (DMA3) INTTC2& INTETC23 INTTC3 enable F2H ITC3C R 0 INTTC4& INTETC45 INTTC5 enable ITC5C R 0 INTTC6& INTETC67 INTTC7 enable ITC7C R 0 - - INTTC2 (DMA2) INTTC5 (DMA5) F3H INTTC4 (DMA4) INTTC7 (DMA7) F4H INTTC6 (DMA6) INTWDT INTWD F7H Always write "0". Interrupt request flag IxxM2 0 0 0 0 1 1 1 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 92C820-47 2007-02-16 TMP92C820 (2) External interrupt control Symbol Name Address 7 6 5 I3EDGE W Interrupt IIMC input mode control F6H (Prohibit RMW) 0 0: Rising 1: Falling 4 I2EDGE W 0 0: Rising 1: Falling 3 I1EDGE W 0 0: Rising 1: Falling 2 I0EDGE W 0 0: Rising 1: Falling 1 I0LE R/W 0 0: Edge mode 1: Level mode 0 - R/W 0 Always write "0". INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 *INT0 level enable 0 1 Edge detect INT "H" level INT Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense. Setting example: DI LD LD EI (IIMC), XXXXXX0 - B (INTCLR), 0AH ; ; Switches from level to edge. Clears interrupt request flag. Note 2: X: Don't care, -: No change Note 3: See electrical characteristics in section 4 for external interrupt input pulse width. Settings of External Interrupt Pin Function Interrupt INT0 Pin Name PC3 Mode Rising edge Falling edge High level Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Setting Method IIMC INT1 INT2 INT3 PC1 PC5 PC6 92C820-48 2007-02-16 TMP92C820 (3) SIO receive interrupt control Symbol Name Address 7 6 5 4 3 2 IR2LE W SIO SIMC interrupt mode control 1 F5H (Prohibit RMW) edge mode level mode 1 IR1LE W 1 edge mode level mode 0 IR0LE W 1 edge mode level mode 0: INTRX2 0: INTRX1 0: INTRX0 1: INTRX2 1: INTRX1 1: INTRX0 INTRX0 rising edge enable 0 1 Rising edge detect INTRX0 "H" level INTRX0 INTRX1 level enable 0 1 Rising edge detect INTRX1 "H" level INTRX1 INTRX2 level enable 0 1 Rising edge detect INTRX2 "H" level INTRX2 92C820-49 2007-02-16 TMP92C820 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1 to the register INTCLR. 8H For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH ; Clears interrupt request flag INT0. Symbol Name Interrupt clear control Address F8H (Prohibit RMW) 7 CLRV7 6 CLRV6 0 5 CLRV5 0 4 CLRV4 W 0 3 CLRV3 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 INTCLR 0 Interrupt vector (5) Micro DMA start vector registers These registers assign micro DMA processing to an sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel's micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.) 92C820-50 2007-02-16 TMP92C820 Symbol Name DMA0 start vector Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 R/W 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA0V 100H 0 DMA1V5 DMA0 start vector DMA1 start vector R/W 0 DMA2V5 DMA2V DMA2 start vector 102H 0 DMA1 start vector R/W DMA2 start vector DMA3V5 DMA3V DMA3 start vector 103H 0 DMA4V5 DMA4V DMA4 start vector 104H 0 DMA5V5 DMA5V DMA5 start vector 105H 0 DMA6V5 DMA6V DMA6 start vector 106H 0 DMA7V5 DMA7V DMA7 start vector 107H 0 DMA3V4 0 DMA4V4 0 DMA5V4 0 DMA6V4 0 DMA7V4 0 DMA3V3 0 DMA4V3 0 DMA5V3 0 DMA6V3 0 DMA7V3 0 DMA3V2 0 DMA4V2 0 DMA5V2 0 DMA6V2 0 DMA7V2 0 DMA3V1 0 DMA4V1 0 DMA5V1 0 DMA6V1 0 DMA7V1 0 DMA3V0 0 DMA4V0 0 DMA5V0 0 DMA6V0 0 DMA7V0 0 DMA1V 101H R/W DMA3 start vector R/W DMA4 start vector R/W DMA5 start vector R/W DMA6 start vector R/W DMA7 start vector 92C820-51 2007-02-16 TMP92C820 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name DMA burst Address 7 DBST7 6 DBST6 0 5 DBST5 0 4 DBST4 R/W 0 3 DBST3 0 2 DBST2 0 1 DBST1 0 0 DBST0 0 DMAB 108H 0 1: DMA request on Burst mode 92C820-52 2007-02-16 TMP92C820 (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, if immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid this, an instruction which clears an interrupt request flag should always be preceded by a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 3-instructions (e.g., "NOP" x 3 times). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register INT0 level mode In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H NOP NOP NOP EI INTRX In edge mode (The register SIMC Note: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input changes from high to low after an interrupt request has been generated in level mode. ("H" "L") INTRX: Instructions which read the receive buffer. 92C820-53 2007-02-16 TMP92C820 3.5 Function of Ports TMP92C820 has I/O port pins that are shown in Table 3.5.1. In addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table 3.5.2 lists I/O registers and their specifications. 0H 1H Table 3.5.1 Port Functions (1/2) (R: PU = with programmable pull-up resistor, U = with pull-up resistor) Port Name Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Pin Name P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 P71 P72 P73 P74 P75 P76 Number of Pins 8 8 8 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O* I/O* I/O* Output Output Output Output Output Output I/O Output Output Output Output Output Output Output Output I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - - - - - - - - - - - - - - - - - - - - - - - - - - - U - - - - - - - - - - - I/O Setting Bit Bit Bit Bit* Bit* Bit* (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Name for Built-in Function D8 to D15 D16 to D23 D24 to D31 A0 to A7 A8 to A15 A16 to A23 RD WRLL WRLU WRUL WRUU R/ W WAIT CS0 , SDCSH CS1 , SDCSL CS2 , CS2A CS3 Port 8 P80 P81 P82 P83 P84 P85 P86 P87 EA24, CS2B EA25, CS2C CS2D SDCLK SCK SO, SDA SI, SCL CS2E CS2F CS2G , TXD2 CSEXA , RXD2 Port 9 P90 P91 P92 P93 P94 P95 P96 Port A Port C PA0 to PA7 PC0 PC1 PC3 PC5 PC6 KI0 to KI7 TA0IN INT1, TA1OUT INT0 INT2, TA3OUT INT3, TB0OUT0 TXD0 RXD0 SCLK0, CTS0 TXD1 RXD1 SCLK1, CTS1 Port F PF0 PF1 PF2 PF3 PF4 PF5 *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. 92C820-54 2007-02-16 TMP92C820 Table 3.5.1 Port Functions (2/2) (R: PU = with programmable pull-up resistor, U = with pull-up resistor) Port Name Port G Port J Pin Name PG0 to PG4 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 Number of Pins 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 I/O Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output I/O R - - - - - - - - - - - - - - - - I/O Setting (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Pin Name for Built-in Function AN0 to AN4, ADTRG (PG3) SDRAS SDCAS SDWE , SRWR SDLLDQM , SRLLB SDLUDQM , SRLUB SDULDQM , SRULB SDUUDQM , SRUUB SDCKE D1BSCP D2BLP D3BFR DLEBCD DOFFB ALARM , MLDALM Port K PK0 PK1 PK2 PK3 PK4 PK6 Port L PL0 to PL7 LD0 to LD7 92C820-55 2007-02-16 TMP92C820 Table 3.5.2 I/O Registers and Specifications (1/3) Port Port 1 Pin Name P10 to P17 Input port Output port Specification Pn X X X X X X X X X X X X X X X X X X X 0 1 X 0 1 X 0 1 X 0* 1* 0 0* 1* 0 0* 1* 0 None I/O Register PnCR PnFC PnFC2 PnODE 0 1 0 1 0 1 0 1 0 1 0 1 0 None None None None None None None None None None None None D8 to D15 bus Port 2 P20 to P27 Input port Output port D16 to D23 bus Port 3 P30 to P37 Input port Output port D24 to D31 bus Port 4 P40 to P47 Input port* Output port* A0 to A7 output Port 5 P50 to P57 Input port* Output port* A8 to A15 output Port 6 P60 to P67 Input port* Output port* A16 to A23 output Port 7 P70 to P75 P70 P71 P72 P73 P74 P75 P76 Output port RD output WRLL output WRLU output WRUL output WRUU output X None 1 None None R/ W output Input port Output port WAIT input X X X X X X X X X X X X X X X X 0 1 0 0 0 1 0 1 1 X 1 X 1 1 X 1 X X 1 0 0 0 1 0 1 0 0 1 0 1 1 0 Port 8 P80 to P87 P80 P81 P82 P83 P84 P85 P86 P87 Output port CS0 output CS1 output SDCS output CS2 output CS2A output CS3 output EA24 output CS2B output EA25 output CS2C output CS2D output SDCLK output None None X: Don't care *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. 92C820-56 2007-02-16 TMP92C820 Table 3.5.2 I/O Registers and Specifications (2/3) Port Port 9 Pin Name P90 to P96 P90 P91 P92 P93 Input port Output port SCK input Specification Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 X 0 1 0 1 X X 1 1 X 1 1 1 1 X 1 1 X X X 0 1 0 X 1 X 0 X 1 0 0 0 1 0 0 0 1 0 0 1 0 None 0 1 X 1 0 0 0 1 0 1 0 1 0 1 0 0/1 0 0 1 0 0/1 0 None I/O Register PnCR PnFC PnFC2 PnODE 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 None 1 1 1 1 None 1 1 None None None None None None None 0 0 0 0/1 0/1 1 0 1 X X 0 1 X X 0 1 X 0 1 X X None SCK output SO output SDA SI input SCL CS2E output P94 SSCMD input SSCMD output SSCMD (Open drain) CS2F output SSDAT input SSDAT output SSDAT (Open drain) CS2G output TXD2 output TXD2 (Open drain) CSEXA output RXD2 input Input port KI0 to KI7 input Input port Output port TA0IN input TA1OUT output INT1 input INT0 input INT2 input TA3OUT INT3 input TB0OUT0 Input port Output port TXD0 TXD0 (Open drain) RXD0 input SCLK0 input/output CTS0 input TXD1 TXD1 (Open drain) RXD1 input SCLK1 input/output CTS1 input Input port AN0 to AN4 input ADTRG input P95 P96 Port A Port C PA0 to PA7 PC0, PC1, PC3 PC5, PC6 PC0 PC1 PC3 PC5 PC6 Port F PF0 to PF5 PF0 PF1 PF2 PF3 PF4 PF5 Port G PG0 to PG4 PG3 None None X: Don't care 92C820-57 2007-02-16 TMP92C820 Table 3.5.2 I/O Registers and Specifications (3/3) Port Port J Pin Name PJ0 to PJ7 PJ0 PJ1 PJ2 PJ3 Specification Pn Output port SDRAS output SDCAS output SDWE output SRWR output I/O Register PnCR PnFC PnFC2 PnODE 0 1 1 1 X 1 X None 1 X 1 X 1 X 1 0 1 1 None 1 1 1 1 1 0 0 1 None None None None 0 0 0 0 1 0 1 0 1 0 1 0 1 0 None X X X X X X X X X X X X X X X X X X X X 1 0 X X X SDLLDQM output SRLLB output PJ4 SDLUDQM output SRLUB output PJ5 SDULDQM output SRULB output PJ6 SDUUDQM output SRUUB output Port K PJ7 PK0 to PK6 PK0 PK1 PK2 PK3 PK4 PK6 SDCKE output Output port D1BSCP output D2BLP output D3BFR output DLEBCD output DOFFB output ALARM output MLDALM output Input port Output port LD0 to LD7 output Port L PL0 to PL7 0 1 X X: Don't care After a reset the port pins listed below function as general-purpose I/O port pins. A reset sets I/O pins, which can be programmed for either input, or output to be input ports pins. Setting the port pins for internal function use must be done in software. 92C820-58 2007-02-16 TMP92C820 3.5.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port 1 can also function as a data bus (D8 to D15). AM1 AM0 0 0 1 1 0 1 0 1 Reset Function Setting after Reset is Released Don't use this setting Data bus (D8 to D15) Data bus (D8 to D15) Don't use this setting Direction control (on bit basis) P1CR write Function control (on bit basis) Internal data bus External access (Data write) P1FC write S Output latch A Selector P1 write D8 to D15 Output buffer B Port 1 P10 to P17 (D8 to D15) P1 read External access (Data read) Figure 3.5.1 Port 1 92C820-59 2007-02-16 TMP92C820 Port 1 Register 7 P1 (0004H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0) Port 1 Control Register 7 P1CR (0006H) Bit symbol Read/Write After reset Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C W 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 Refer to port 1 function setting Port 1 Function Register 7 P1FC (0007H) Bit symbol Read/Write After reset Function 6 5 4 3 2 1 0 P1F W 1 Refer to port 1 function setting Port 1 function register Note 1:Read-modify-write is prohibited for the registers P1CR and P1FC. Note 2: Figure 3.5.2 Register for Port 1 92C820-60 2007-02-16 TMP92C820 3.5.2 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P2CR and function register P2FC. In addition to functioning as a general-purpose I/O port, port 2 can also function as a data bus (D16 to D23). Function Setting after Reset is Released Don't use this setting Input port Data bus (D16 to D23) Don't use this setting AM1 AM0 0 0 1 1 0 1 0 1 Reset Direction control (on bit basis) P2CR write Function control (on bit basis) Internal data bus External access (Data write) P2FC write S Output latch A Selector P2 write D16 to D23 Output buffer B Port 2 P20 to P27 (D16 to D23) P2 read External access (Data read) Figure 3.5.3 Port 2 92C820-61 2007-02-16 TMP92C820 Port 2 Register 7 P2 (0008H) Bit symbol Read/Write After reset P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Data from external port (Output latch register is cleared to 0) Port 2 Control Register 7 P2CR (000AH) Bit symbol Read/Write After reset Function 0 0 0 0 P27C 6 P26C 5 P25C 4 P24C W 3 P23C 0 2 P22C 0 1 P21C 0 0 P20C 0 0: Input 1: Output Port 2 Function Register 7 P2FC (000BH) Bit symbol Read/Write After reset Function 6 5 4 3 2 1 0 P2F W 0/1 Note2 0: Port 1: Data bus (D16 to D23) Port 2 function register Note 1:Read-modify-write is prohibited for the registers P2CR and P2FC. Note 2: It is set to "Port" or "Data bus" by AM pin setting. Note 3: Data bus (D16 to D23) Figure 3.5.4 Register for Port 2 92C820-62 2007-02-16 TMP92C820 3.5.3 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P3CR and function register P3FC. In addition to functioning as a general-purpose I/O port, port 3 can also function as a data bus (D24 to D31). AM1 AM0 0 0 1 1 0 1 0 1 Reset Function Setting after Reset is Released Don't use this setting Input port Data bus (D24 to D31) Don't use this setting Direction control (on bit basis) P3CR write Function control (on bit basis) Internal data bus External access (Data write) P3FC write S Output latch A Selector P3 write D24 to D31 Output buffer B Port 3 P30 to P37 (D24 to D31) P3 read External access (Data read) Figure 3.5.5 Port 3 92C820-63 2007-02-16 TMP92C820 Port 3 Register 7 P3 (000CH) Bit symbol Read/Write After reset P37 6 P36 5 P35 4 P34 R/W 3 P33 2 P32 1 P31 0 P30 Data from external port (Output latch register is cleared to 0) Port 3 Control Register 7 P3CR (000EH) Bit symbol Read/Write After reset Function 0 0 0 0 P37C 6 P36C 5 P35C 4 P34C W 3 P33C 0 2 P32C 0 1 P31C 0 0 P30C 0 0: Input 1: Output Port 3 Function Register 7 P3FC (000FH) Bit symbol Read/Write After reset Function 6 5 4 3 2 1 0 P3F W 0/1 Note2 0: Port 1: Data bus (D24 to D31) Port 3 function register Note 1:Read-modify-write is prohibited for the registers P3CR and P3FC. Note 2: It is set to "Port" or "Data bus" by AM pin setting. Note 3: Figure 3.5.6 Register for Port 3 92C820-64 2007-02-16 TMP92C820 3.5.4 Port 4 (P40 to P47) Port 4 is an 8-bit general-purpose I/O ports*. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC*. In addition to functioning as a general-purpose I/O port, port 4 can also function as an address bus (A0 to A7). AM1 AM0 0 0 1 1 0 1 0 1 Reset Internal address bus A0 to A7 Direction control (on bit basis)* Function Setting after Reset is Released Don't use this setting Address bus (A0 to A7) Address bus (A0 to A7) Don't use this setting P4CR write Internal data bus Function control (on bit basis) S B P4FC write Selector Output buffer Output latch A Port 4 P40 to P47 (A0 to A7) P4 write P4 read *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.7 Port 4 92C820-65 2007-02-16 TMP92C820 Port 4 Register 7 P4 (0010H) Bit symbol Read/Write After reset P47 6 P46 5 P45 4 P44 R/W 3 P43 2 P42 1 P41 0 P40 Data from external port (Output latch register is cleared to 0) Port 4 Control Register 7 P4CR (0012H) Bit symbol Read/Write After reset Function 0 0 0 0 P47C 6 P46C 5 P45C 4 P44C W 3 P43C 0 2 P42C 0 1 P41C 0 0 P40C 0 0: Input 1: Output (Note2) Port 4 Function Register 7 P4FC (0013H) Bit symbol Read/Write After reset Function 1 1 1 1 P47F 6 P46F 5 P45F 4 P44F W 3 P43F 1 2 P42F 1 1 P41F 1 0 P40F 1 0: Port 1: Address bus (A0 to A7) (Note2) Note1: Read-modify-write is prohibited for the registers P4CR and P4FC. Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.8 Port 4 Registers 92C820-66 2007-02-16 TMP92C820 3.5.5 Port 5 (P50 to P57) Port 5 is an 8-bit general-purpose I/O ports*. Bits can be individually set as either inputs or outputs by control register P5CR and function register P5FC*. In addition to functioning as a general-purpose I/O port, port 5 can also function as an address bus (A8 to A15). AM1 AM0 0 0 1 1 0 1 0 1 Reset Internal address bus A8 to A15 Direction control (on bit basis)* Function Setting after Reset is Released Don't use this setting Address bus (A8 to A15) Address bus (A8 to A15) Don't use this setting P5CR write Internal data bus Function control (on bit basis) S B P5FC write Selector Output buffer Output latch A Port 5 P50 to P57 (A8 to A15) P5 write P5 read *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.9 Port 5 92C820-67 2007-02-16 TMP92C820 Port 5 Register 7 P5 (0014H) Bit symbol Read/Write After reset P57 6 P56 5 P55 4 P54 R/W 3 P53 2 P52 1 P51 0 P50 Data from external port (Output latch register is cleared to 0) Port 5 Control Register 7 P5CR (0016H) Bit symbol Read/Write After reset Function 0 0 0 0 P57C 6 P56C 5 P55C 4 P54C W 3 P53C 0 2 P52C 0 1 P51C 0 0 P50C 0 0: Input 1: Output (Note2) Port 5 Function Register 7 P5FC (0017H) Bit symbol Read/Write After reset Function 1 1 1 1 P57F 6 P56F 5 P55F 4 P54F W 3 P53F 1 2 P52F 1 1 P51F 1 0 P50F 1 0: Port 1: Address bus (A8 to A15) (Note2) Note1: Read-modify-write is prohibited for the registers P5CR and P5FC. Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.10 Register for Port 5 92C820-68 2007-02-16 TMP92C820 3.5.6 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O ports*. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC*. In addition to functioning as a general-purpose I/O port, port 6 can also function as an address bus (A16 to A23). AM1 AM0 0 0 1 1 0 1 0 1 Reset Internal address bus A16 to A23 Direction control (on bit basis)* Function Setting after Reset is Released Don't use this setting Address bus (A16 to A23) Address bus (A16 to A23) Don't use this setting P6CR write Internal data bus Function control (on bit basis) S B P6FC write Selector Output buffer Output latch A Port 6 P60 to P67 (A16 to A23) P6 write P6 read *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.11 Port 6 92C820-69 2007-02-16 TMP92C820 Port 6 Register 7 P6 (0018H) Bit symbol Read/Write After reset P67 6 P66 5 P65 4 P64 R/W 3 P63 2 P62 1 P61 0 P60 Data from external port (Output latch register is cleared to 0) Port 6 Control Register 7 P6CR (001AH) Bit symbol Read/Write After reset Function 0 0 0 0 P67C 6 P66C 5 P65C 4 P64C W 3 P63C 0 2 P62C 0 1 P61C 0 0 P60C 0 0: Input 1: Output (Note2) Port 6 Function Register 7 P6FC (001BH) Bit symbol Read/Write After reset Function 1 1 1 1 P67F 6 P66F 5 P65F 4 P64F W 3 P63F 1 2 P62F 1 1 P61F 1 0 P60F 1 0: Port 1: Address bus (A16 to A23) (Note2) Note1: Read-modify-write is prohibited for the registers P6CR and P6FC. Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.12 Port 6 Registers 92C820-70 2007-02-16 TMP92C820 3.5.7 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port (P70 to P75 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P75 pins can also function as read/write strobe signals to connect with an external memory. P76 pin can also function as wait input. A reset initializes P70 to P75 pins to output port mode, and P76 pin to input port mode. AM1 AM0 0 0 1 1 0 1 0 1 Function Setting after Reset is Released Don't use this setting RD pin RD pin Don't use this setting Reset Function control (on bit basis) Internal data bus P7FC write S Output latch A Selector P7 write B Output buffer P70 ( RD ) P7 read RD Figure 3.5.13 Port 7 (P70) 92C820-71 2007-02-16 TMP92C820 Reset Function control (on bit basis) Internal data bus P7FC write S Output latch A Selector P7 write B Output buffer P71 ( WRLL ) P72 ( WRLU ) P73 ( WRUL ) P74 ( WRUU ) P7 read WRLL , WRLU , WRUL , WRUU Figure 3.5.14 Port 7 (P71 to P74) Reset Function control (on bit basis) Internal data bus P7FC write S Output latch A Selector P7 write B Output buffer P75 (R/ W ) P7 read R/ W Figure 3.5.15 Port 7 (P75) 92C820-72 2007-02-16 TMP92C820 Reset Function control (on bit basis) P7FC write Direction control (on bit basis) P7CR write Internal data bus S Output latch Output buffer P7 write P76 ( WAIT ) P7 read Internal wait signal Figure 3.5.16 Port 7 (P76) 92C820-73 2007-02-16 TMP92C820 Port 7 Register 7 P7 (001CH) Bit symbol Read/Write After reset Data from external port (Note) 1 1 6 P76 5 P75 4 P74 3 P73 R/W 1 2 P72 1 1 P71 1 0 P70 1 Note: Output latch register is cleared to 0. Port 7 Control Register 7 P7CR (001EH) Bit symbol Read/Write After reset Function 6 P76C W 0 0: Input 1: Output 5 4 3 2 1 0 Port 7 Function Register P7FC (001FH) 7 Bit symbol Read/Write After reset Function 6 P76F 0 0: Port 1: WAIT 5 P75F 0 0: Port 1: R/ W 4 P74F 0 0: Port 1: WRUU 3 P73F W 0 0: Port 1: WRUL 2 P72F 0 0: Port 1: WRLU 1 P71F 0 0: Port 1: WRLL 0 P70F 1 0: Port 1: RD Note: Read-modify-write is prohibited for the registers P7CR and P7FC. Figure 3.5.17 Register for Port 7 92C820-74 2007-02-16 TMP92C820 3.5.8 Port 8 (P80 to P87) Ports 80 to 87 are 8-bit output ports. Resetting sets output latch of P82 to "0" and output latches of P80 to P81, P83 to P87 to "1". Port 8 also function as chip-select output ( CS0 to CS3 ), extend address output (EA24, EA25), extend chip-select output ( CS2A , CS2B , CS2C , CS2D ), port 8 also function as output pin for SDRAM controller ( SDCSL , SDCSH , SDCLK), Above setting is used the function register P8FC. Writing "1" in the corresponding bit of P8FC, P8FC2 enables the respective functions. Resetting resets P87F of P8FC to "1", P80F to P86F of P8FC to "0", and P8FC2 to "0", sets all bits to output ports. Reset Function control 2 (on bit basis) P8FC2 write Internal data bus Function control (on bit basis) P8FC write S Output lacth A Selector B P8 write C P80 ( CS0 , SDCSH ) P81 ( CS1 , SDCSL ) P82 ( CS2 , CS2A ) P83 ( CS3 ) P84 (EA24, CS2B ) P85 (EA25, CS2C ) P86 ( CS2D ) P87 (SDCLK) SDCSH , SDCSL , CS2A , "1", CS2B , CS2C , CS2D , "1" P8 read CS0 , CS1 , CS2 , CS3 , EA24, EA25, "1", SDCLK Figure 3.5.18 Port 8 92C820-75 2007-02-16 TMP92C820 Port 8 Register 7 P8 (0020H) Bit symbol Read/Write After reset 1 1 1 1 P87 6 P86 5 P85 4 P84 R/W 3 P83 1 2 P82 0 1 P81 1 0 P80 1 Port 8 Function Register 7 P8FC (0023H) Bit symbol Read/Write After reset Function 1 0: Port 1: SDCLK 0 Always write "0". 0 0: Port 1: EA25 0 0: Port 1: EA24 P87F 6 - 5 P85F 4 P84F W 3 P83F 0 0: Port 1: CS3 2 P82F 0 0: Port 1: CS2 1 P81F 0 0: Port 1: CS1 0 P80F 0 0: Port 1: CS0 Port 8 Function Register 2 7 P8FC2 (0021H) Bit symbol Read/Write After reset Function 0 Always write "0". 0 0: 6 P86F2 5 P85F2 4 P84F2 W 3 - 0 Always write "0". 2 P82F2 0 0: 1 P81F2 0 0: 0 P80F2 0 0: Note :Read-modify-write is prohibited for P8FC and P8FC2 . Figure 3.5.19 Registers for Port 8 92C820-76 2007-02-16 TMP92C820 3.5.9 Port 9 (P90 to P96) P90 to P96 are 7-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets port 9 to input port and all bits of output latch to "1". Writing in the corresponding bit of P9FC enables the respective functions. Resetting resets the P9FC to "0", and sets all bits to input ports. (1) Port 90 (SCK), port 91 (SO/SDA), and port 92 (SI/SCL) Ports 90 to 92 are general-purpose I/O port. It is also used as SCK (Clock signal for SIO mode), SO (Data output for SIO mode), SDA (Data input for I2C mode), SI (Data input for SIO mode), and SCL (Clock input/output for I2C mode) for serial bus interface. Reset Direction control (on bit basis) P9CR write Internal data bus Function control (on bit basis) P9FC write S Output latch P90 (SCK) P91 (SO/SDA) P92 (SI/SCL) Open-drain possible P9ODE S A Selector B P9 write SCK output SO output SDA output SCL output Figure 3.5.20 Port 9 (P90 to P92) 92C820-77 2007-02-16 TMP92C820 (2) Ports 93 ( CS2E ), 94 ( CS2F ), 95 (TXD2, CS2G ), and 96 (RXD2, CSEXA ) Ports 93 to 96 are general-purpose I/O ports. Reset Direction control (on bit basis) P9CR write Internal data bus Function control (on bit basis) P9FC write S Output latch P93 ( CS2E ) P94 ( CS2F ) P95 (TXD2, CS2G ) Open-drain possible P9ODE P9 write TXD2 CS2E , CS2F , CS2G S A Selector B C S B Selector (Except P95) P9 read A Figure 3.5.21 Port 9 (P93 to P95) Reset Direction control (on bit basis) P9CR write Internal data bus Function control (on bit basis) P9FC write S Output latch S A Selector B S B Selector P96 (RXD2, CSEXA ) P9 write CSEXA P9 read RXD2 A Figure 3.5.22 Port 9 (P96) 92C820-78 2007-02-16 TMP92C820 Port 9 Register 7 P9 (0024H) Bit symbol Read/Write After reset 6 P96 5 P95 4 P94 3 P93 R/W 2 P92 1 P91 0 P90 Data from external port (Output latch register is set to 1) Port 9 Control Register 7 P9CR (0026H) Bit symbol Read/Write After reset Function 0 0 0 6 P96C 5 P95C 4 P94C 3 P93C W 0 0: Input 1: Output 2 P92C 0 1 P91C 0 0 P90C 0 Port 9 Function Register 7 P9FC (0027H) Bit symbol Read/Write After reset Function 0 0: Port 1: RXD2, CSEXA 6 P96F 5 P95F 0 0: Port 1: TXD2, CS2G 4 P94F 0 0: Port 1: CS2F 3 P93F W 0 0: Port 1: CS2E 2 P92F 0 0: Port, SI, 1: SCL Note 2 1 P91F 0 0: Port 1: SO, SDA 0 P90F 0 0: Port, SCK input 1: SCK Output Note 2 CS2E setting 0 Input port (Reserved) 1 Output port CS2E 0 1 CS2F setting 0 Input port (Reserved) 1 Output port CS2F 0 1 TXD2, CS2G setting 0 Input port TXD2 1 Output port CS2G 0 1 Port 9 ODE Register 7 P9ODE (0025H) Bit symbol Read/Write After reset Function 6 5 P95ODE W 0 0: 3 states 1: Open drain 4 - W 0 Always write "0". 3 - W 0 Always write "0". 2 P92ODE W 0 0: 3 states 1: Open drain 1 P91ODE W 0 0: 3 states 1: Open drain 0 Note 1: Read-modify-write is prohibited for P9CR, P9FC, and P9ODE. Note 2: When using SI and SCK input function, set P9FC Figure 3.5.23 Register for Port 9 92C820-79 2007-02-16 TMP92C820 3.5.10 Port A (PA0 to PA7) Ports A0 to A7 are 8-bit input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, ports A0 to A7 can also key-on wakeup function as keyboard interface. The various functions can each be enabled by writing a "1" to the corresponding bit of the port A function register (PAFC). Resetting resets all bits of the register PAFC to "0" and sets all pins to be input port. INTKEY Start edge detection Internal data bus PA0 to PA7 8-input OR Reset Key-on enable (on bit basis) PAFC write PA0 to PA7 (KI0 to KI7) PA read Pull-up resistor Figure 3.5.24 Port A When PAFC = "1", if either of input of KI0 to KI7 pins falls down, INTKEY interrupt is generated. INTKEY interrupt can be used release all HALT mode. 92C820-80 2007-02-16 TMP92C820 Port A Register 7 PA (0028H) Bit symbol Read/Write After reset PA7 6 PA6 5 PA5 4 PA4 R 3 PA3 2 PA2 1 PA1 0 PA0 Data from external port Port A Function Register 7 PAFC (002BH) Bit symbol Read/Write After reset Function 0 0 0 0 PA7F 6 PA6F 5 PA5F 4 PA4F W 3 PA3F 0 2 PA2F 0 1 PA1F 0 0 PA0F 0 0: KEY-IN disable 1: KEY-IN enable Key-IN of Port A 0 1 Note: Read-modify-write is prohibited for the registers PAFC. Disable Enable Figure 3.5.25 Register for Port A 92C820-81 2007-02-16 TMP92C820 3.5.11 Port C (PC0, PC1, PC3, PC5 and PC6) Port C is 5-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port C to be an input port. In addition to functioning as a general-purpose I/O port, port C can also functions as I/O pin for timers (TA0IN, TA1OUT, TA3OUT, TB0OUT0), input pin for external interruption (INT0 to INT3). Above setting is used the function register PCFC and PCCR register. Edge select of external interruption establishes it with IIMC register, which there is in interruption controller. Resetting resets bits of the register PCCR and PCFC to "0" and sets all pins to be input port. (1) PC0 (TA0IN) In addition to function as I/O port, port 0 can also function as input pin TA0IN of timer channel 0. Reset Direction control (on bit basis) PCCR write Internal data bus Function control (on bit basis) PCFC write S Output latch PC0 (TA0IN) PC write S B Selector A PC read TA0IN Figure 3.5.26 Port C (PC0) Note: Cannot read the output latch data when output mode. 92C820-82 2007-02-16 TMP92C820 (2) PC1 (INT1, TA1OUT), PC5 (INT2, TA3OUT) and PC6 (INT3, TB0OUT0) Reset Direction control (on bit basis) PCCR write Internal data bus Function control (on bit basis) PCFC write S Output latch TA1OUT PC write TA3OUT TB0OUT0 A S PC1 (INT1, TA1OUT) PC5 (INT2, TA3OUT) PC6 (INT3, TB0OUT0) S B Selector A Rising/falling edge detection Selector B PC read INT1 INT2 INT3 IIMC Figure 3.5.27 Port C (PC1, PC5, PC6) Note: Cannot read the output latch data when output mode. 92C820-83 2007-02-16 TMP92C820 (3) PC3 (INT0) Reset Direction control (on bit basis) PCCR write Internal data bus Function control (on bit basis) PCFC write S Output latch PC3 (INT0) PC write S B Selector A Level/edge select and Rising/falling select IIMC PC read INT0 Figure 3.5.28 Port C (PC3) 92C820-84 2007-02-16 TMP92C820 Port C Register 7 PC (0030H) Bit symbol Read/Write After reset 6 PC6 R/W 5 PC5 4 3 PC3 R/W Data from external port (Output latch register is set to 1) 2 1 PC1 R/W 0 PC0 Data from external port (Output latch register is set to 1) Data from external port (Output latch register is set to 1) Port C Control Register 7 PCCR (0032H) Bit symbol Read/Write After reset Function 0 6 PC6C W 5 PC5C 0 4 3 PC3C W 0 0: Input 1: Output 2 1 PC1C W 0 0 PC0C 0 0: Input 1: Output 0: Input 1: Output Port C Function Register 7 PCFC (0033H) Bit symbol Read/Write After reset Function 0 0: Port 1: INT3 TB0OUT0 6 PC6F W 5 PC5F 0 0: Port 1: INT2 TA3OUT 4 3 PC3F W 1 0: Port 1: INT0 2 1 PC1F W 0 0: Port 1: INT1 TA1OUT 0 PC0F 0 0: Port 1: TA0IN INT1, TA1OUT setting 0 Input port INT1 1 Output port TA1OUT 0 1 INT2, TA3OUT setting 0 Input port INT2 1 Output port TA3OUT 0 1 INT3, TB0OUT0 setting 0 Input port INT3 1 Output port TB0OUT0 0 1 Note 1: Read-modify-write is prohibited for the registers PCCR and PCFC. Note 2: PC0/TA0IN pin does not have a register changing port/function. For example, when it is used as an input port, the input signal is inputted to 8-bit timer. Note 3: Cannot read the output latch data when PC0, PC1, PC5, and PC6 are output mode. Figure 3.5.29 Register for Port C 92C820-85 2007-02-16 TMP92C820 3.5.12 Port F (PF0 to PF5) Ports F0 to F5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PF0 to PF5 to be an input ports. It also sets all bits of the output latch register to "1". In addition to functioning as general-purpose I/O port pins, PF0 to PF5 can also function as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing a "1" to the corresponding bit of the port F function register (PFFC). By resetting, clears all bits of the registers PFCR and PFFC to 0 and sets all pins to be input ports. (1) Ports PF0 (TXD0) and PF3 (TXD1) As well as functioning as I/O port pins, port PF0 and PF3 can also function as serial channel TXD output pins. Reset Direction control (on bit basis) PFCR write Internal data bus Function control (on bit basis) PFFC write S Output latch S A Selector B S B Selector PF0 (TXD0) PF3 (TXD1) Open-drain set possible PF write TXD0, TXD1 PF read A Figure 3.5.30 Port F (PF0 and PF3) 92C820-86 2007-02-16 TMP92C820 (2) Ports PF1 and PF4 (RXD0, RXD1) Ports PF1 and PF4 are I/O port pins and can also is used as RXD input for the serial channels. Reset Direction control (on bit basis) PFCR write Internal data bus S Output latch PF1 (RXD0) PF4 (RXD1) PF write S B Selector PF read RXD0, RXD1 A Figure 3.5.31 Port F (PF1 and PF4) 92C820-87 2007-02-16 TMP92C820 (3) Ports PF2 ( CTS0 , SCLK0) and PF5 ( CTS1 , SCLK1) Ports PF2 and PF5 are I/O port pins and can also be used as CTS input or SCLK input/output for the serial channels. Reset Direction control (on bit basis) PFCR write Internal data bus Function control (on bit basis) PFFC write S Output latch S A Selector B S B Selector PF2 (SCLK0, CTS0 ) PF5 (SCLK1, CTS1 ) PF write SCLK0, SCLK1 output PF read CTS0 , CTS1 SCLK0, SCLK1 input A Figure 3.5.32 Port F (PF2 and PF5) 92C820-88 2007-02-16 TMP92C820 Port F Register 7 PF (003CH) Bit symbol Read/Write After reset 6 5 PF5 4 PF4 3 PF3 R/W 2 PF2 1 PF1 0 PF0 Data from external port (Output latch register is set to 1) Port F Control Register 7 PFCR (003EH) Bit symbol Read/Write After reset Function 0 0 0 6 5 PF5C 4 PF4C 3 PF3C W 2 PF2C 0 1 PF1C 0 0 PF0C 0 0: Input 1: Output Port F Function Register 7 PFFC (003FH) Bit symbol Read/Write After reset Function 6 5 PF5F W 0 0: Port 1: SCLK1 output 4 3 PF3F W 0 0: Port 1: TXD1 2 PF2F 0 0: Port 1: SCLK0 output 1 0 PF0F W 0 0: Port 1: TXD0 3 states, Open-drain setting 0 Input port TXD1 (Open drain) 1 Output port TXD1 (3 states) 0 1 0 Input port TXD0 (Open drain) 1 Output port TXD0 (3 states) 0 1 Note 1: Note 2: Note 3: Read-modify-write is prohibited for the registers PFCR and PFFC. PF1/RXD0 and PF4/RXD1 pins do not have a register changing Port/Function. For example, PF1 and PF3 pins dose not have a register changing 3 states/Open drain. when it is used as an input port, the input signal is inputted to SIO as the serial receive data. Figure 3.5.33 Register for Port F 92C820-89 2007-02-16 TMP92C820 3.5.13 Port G (PG0 to PG4) PG0 to PG4 are 5-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the AD converter. Internal data bus PG read Convertion result register AD convertor Channel selector Port G PG0 to PG4 (AN0 to AN4) AD read ADTRG (only PG3) Figure 3.5.34 Port G Port G Register 7 PG (0040H) Bit symbol Read/Write After reset Note: converter mode register ADMOD1. 6 5 4 PG4 3 PG3 2 PG2 R Data from external port 1 PG1 0 PG0 The input channel selection of AD converter and the permission of ADTRG input are set by AD Figure 3.5.35 Register for Port G 92C820-90 2007-02-16 TMP92C820 3.5.14 Port J (PJ0 to PJ7) PJ0 to PJ7 are 8-bit output port. Resetting sets the output latch PJ to "1" and PJ0 to PJ7 pins output "1". In addition to functioning as output port, port J also functions as output pins for SDRAM ( SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM, SDCKE) and SRAM ( SRWR , SRLLB , SRLUB , SRULB , SRUUB ). Above setting is used the function register PJFC. Reset Function control2 (on bit basis) PJFC2 write Internal data bus Function control (on bit basis) PJFC write Output latch PJ write S A Selector B C Outpt buffer PJ0 ( SDRAS ) PJ1 ( SDCAS ) PJ2 ( SDWE , SRWR ) PJ3 (SDLLDQM, SRLLB ) PJ4 (SDLUDQM, SRLUB ) PJ5 (SDULDQM, SRULB ) PJ6 (SDUUDQM, SRUUB ) PJ7 (SDCKE) "1", "1", SRWR , SRLLB , SRLUB , SRULB , SRUUB , "1" PJ read SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM, SDCKE Figure 3.5.36 Port J 92C820-91 2007-02-16 TMP92C820 Port J Register 7 PJ (004CH) Bit symbol Read/Write After reset 1 1 1 1 PJ7 6 PJ6 5 PJ5 4 PJ4 R/W 3 PJ3 1 2 PJ2 1 1 PJ1 1 0 PJ0 1 Port J Function Register 7 PJFC (004FH) Bit symbol Read/Write After reset Function 0 0: Port 1: SDCKE 0 0: Port 0 0: Port 0 0: Port PJ7F 6 PJ6F 5 PJ5F 4 PJ4F W 3 PJ3F 0 0: Port 2 PJ2F 0 0: Port 1 PJ1F 0 0: Port 1: SDCAS 0 PJ0F 0 0: Port 1: SDRAS 1: SDUUDQM 1: SDULDQM 1: SDLUDQM 1: SDLLDQM 1: SDWE Port J Function Register 2 7 PJFC2 (004DH) Bit symbol Read/Write After reset Function 0 Always write "0". 0 0: 6 PJ6F2 5 PJ5F2 4 PJ4F2 W 3 PJ3F2 0 0: 2 PJ2F2 0 0: 1 - 0 Always write "0". 0 - 0 Always write "0". Note: Read-modify-write is prohibited for the registers PJFC and PJFC2. Figure 3.5.37 Register for Port J 92C820-92 2007-02-16 TMP92C820 3.5.15 Port K (PK0 to PK4, PK6) Port K is 6-bit output port. Resetting sets the output latch PK to "1", and port K pins output to "1". In addition to functioning as output ports, port K also functions as output pins for LCD controller (D1BSCP, D2BLP, D3BFR, DLEBCD and DOFFB), output pins for RTC alarm ( ALARM ) and output pin for melody/alarm generator (MLDALM, MLDALM ). Above setting is used the function register PKFC. Only PK6 has two output function which ALARM and MLDALM . This selection is used PK Reset Internal data bus Function control (on bit basis) PKFC write S Output latch A Selector PK write B D1BSCP, D2BLP, D3BFR, DLEBCD, DOFFB Outpt buffer PK0 (D1BSCP) PK1 (D2BLP) PK2 (D3BFR) PK3 (DLEBCD) PK4 (DOFFB) PK read Figure 3.5.38 Port K (PK0 to PK4) 92C820-93 2007-02-16 TMP92C820 Reset Function control (on bit basis) Internal data bus PKFC write S Output latch S A Selector B PK6 ( ALARM , MLDALM ) PK write PF read MLDALM ALARM S A Selector B Figure 3.5.39 Port K (PK6) Port K Register 7 PK (0050H) Bit symbol Read/Write After reset 6 PK6 R/W 1 5 4 PK4 1 3 PK3 1 2 PK2 R/W 1 1 PK1 1 0 PK0 1 Port K Function Register 7 PKFC (0053H) Bit symbol Read/Write After reset Function 6 PK6F W 0 0: Port 1: ALARM at 5 4 PK4F 0 0: Port 1: DOFFB 3 PK3F 0 0: Port 2 PK2F W 0 0: Port 1 PK1F 0 0: Port 1: D2BLP 0 PK0F 0 0: Port 1: D1BSCP 1: DLEBCD 1: D3BFR Note: Read-modify-write is prohibited for the register PKFC. Figure 3.5.40 Register for Port K 92C820-94 2007-02-16 TMP92C820 3.5.16 Port L (PL0 to PL7) PL0 to PL7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output using the control register PLCR. Resetting, the control register PLCR to "0" and sets port L to input ports. It also sets all bits of the output latch register to "1". In addition to functioning as a general-purpose I/O port, port L can also function as a data bus for LCD controller (LD0 to LD7). Above setting is used the function register PLFC. Reset Direction control (on bit basis) PLCR write Internal data bus Function control (on bit basis) PLFC write S Output latch Port E PL0 to PL7 (LD0 to LD7) S A Selector B S B Selector A PL write LD7 to LD0 PL read Figure 3.5.41 Port L 92C820-95 2007-02-16 TMP92C820 Port L Register 7 PL (0054H) Bit symbol Read/Write After reset PL7 6 PL6 5 PL5 4 PL4 R/W 3 PL3 2 PL2 1 PL1 0 PL0 Data from external port (Output latch register is set to 1) Port L Control Register 7 PLCR (0056H) Bit symbol Read/Write After reset Function 0 0 0 0 PL7C 6 PL6C 5 PL5C 4 PL4C W 3 PL3C 0 2 PL2C 0 1 PL1C 0 0 PL0C 0 0: Input 1: Output Port L Function Register 7 PLFC (0057H) Bit symbol Read/Write After reset Function 0 0 0 0 PL7F 6 PL6F 5 PL5F 4 PL4F W 3 PL3F 0 2 PL2F 0 1 PL1F 0 0 PL0F 0 0: Port 1: Data bus for LCDC (LD7 to LD0) Figure 3.5.42 Register for Port L 92C820-96 2007-02-16 TMP92C820 3.6 Memory Controller Functions TMP92C820 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for 4-block address area (Block 0 to block 5). (2) Connecting memory specifications Specifies SRAM, ROM as memories to connect with the selected address areas. (3) Data bus size selection Whether 8 bits, 16 bits or 32 bits is selected as the data bus size of the respective block address areas. (4) Wait control Wait specification bit in the control register and WAIT input pin control the number of waits in the external bus cycle. Read cycle and write cycle can specify the number of waits individually. The number of waits is controlled in five mode mentioned below. 0 waits, 1 wait, 2 waits, 3 waits N waits (control with WAIT pin) 3.6.1 92C820-97 2007-02-16 TMP92C820 3.6.2 Control Register and Operation after Reset Release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control register The control registers of the memory controller are as follows. * Control register: BnCSH/BnCSL (n = 0 to 3, EX) Sets the basic functions of the memory controller, that is the connecting memory type, the number of waits to be read and written. Memory start address register: MSARn (n = 0 to 3) Sets a start address in the selected address areas. Memory address mask register: MAMR (n = 0 to 3) Sets a block size in the selected address areas. * * In addition to setting of the above-mentioned registers, it is necessary to set the following registers to control ROM page mode access. * Page ROM control register: PMEMCR Sets to executed ROM page mode accessing. (2) Operation after reset release The start data bus size is determined depending on the state of AM1/AM0 pins just after reset release. Then, the external memory is accessed as follows: AM1 0 0 1 1 AM0 0 1 0 1 Start Mode Don't use this setting Start with 16-bit data bus Start with 32-bit data bus Don't use this setting AM1/AM0 pins are valid only just after reset release. In the other cases, the data bus width is set to the value set to BnBUS bit of the control register. After reset, only control register (B2CSH/B2CSL) of the block address area 2 is automatically valid. The data bus width which is specified by AM1/AM0 pin is loaded to the bit to specify the bus width of the control register in the block address area 2. The block address area 2 is set to address 000000H to FFFFFFH after reset. After reset release, the block address areas are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). Then the control register (BnCS) is set. Set the enable bit (BnE) of the control register to "1" to enable the setting. 92C820-98 2007-02-16 TMP92C820 3.6.3 Basic Functions and Register Setting In this section, setting of the block address area, the connecting memory, and the number of waits out of the memory controller's functions are described. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSARn) sets the start address of the block address areas. The memory controller compares between the register value and the address every bus cycles. The address bit which is masked by the memory address mask register (MAMRn) is not compared by the memory controller. The block address area size is determined by setting the memory address mask register. The set value in the register is compared with the block address area on the bus. If the compared result is a match, the memory controller sets the chip select signal ( CSn ) to "low". (i) Setting memory start address register The MS23 to MS16 bits of the memory start address register respectively correspond with addresses A23 to A16. The lower start address A15 to A0 are always set to address 0000H. Therefore the start address of the block address area are set to addresses 000000H to FF0000H every 64 Kbytes. (ii) Setting memory address mask registers The memory address mask register sets whether an address bit is compared or not. Set the register to "0" to compare, or to "1" not to compare. The address bit to be set is depended on the block address area. Block address area 0: A20 to A8 Block address area 1: A21 to A8 Block address area 2 to 3: A22 to A15 The above-mentioned bits are always compared. The block address area size is determined by the compared result. The size to be set depending on the block address area is as follows. Size (bytes) CS Area 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M CS0 CS1 CS2 to CS3 Note: After reset release, only the control register of the block address area 2 is valid. The control register of the block address area 2 has 92C820-99 2007-02-16 TMP92C820 (iii) Example of register setting To set the block address area 512 bytes from address 110000H, set the register as follows. MSAR1 Register 7 Bit symbol Specified value M1S23 0 6 M1S22 0 5 M1S21 0 4 M1S20 1 3 M1S19 0 2 M1S18 0 1 M1S17 0 0 M1S16 1 M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with address A23 to A16. A15 to A0 are set to "0". Therefore setting MSAR1 to the above-mentioned value specifies the start address of the block address area to address 110000H. The start address is set as it is in the other block address areas. MAMR1 Register 7 Bit symbol Specified value M1V21 0 6 M1V20 0 5 M1V19 0 4 M1V18 0 3 M1V17 0 2 M1V16 0 1 M1V15 to M1V9 0 0 M1V8 1 M1V21 to M1V16 and M1V8 bits of the memory address mask register MAMR1 set whether address A21 to A16 and A8 are compared or not. Set the register to "0" to compare, or to "1" not to compare. M1V15 to M1V9 bits set whether address A15 to A9 are compared or not with 1 bit. A23 and A22 are always compared. Setting the above-mentioned compares A23 to A9 with the values set as the start addresses. Therefore 512 bytes of addresses 110000H to 1101FFH are set as the block address area 1, and compared with the addresses on the bus. If the compared result is a match, the chip select signal CS1 is set to "low". The other block address area sizes are specified like this. Similarly, A23 is always compared in block address areas 2 to 3. Whether A22 to A15 are compared or not is set to register. Note: When the set block address area overlaps with the built-in memory area, or both two address areas overlap, the block address area is processed according to priority as follows. Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3 > CSEX also that any accessed areas outside the address spaces set by CS0 to CS3 are processed as the CSEX space. Therefore, settings of CSEX apply for the control of wait cycles, data bus width, etc,. 92C820-100 2007-02-16 TMP92C820 (2) Connection memory specification Setting the BnOM1 to 0 bit of the control register (BnCSH) specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows BnOM1, BnOM0 Bit (BnCSH register) BnOM1 0 0 1 1 BnOM0 0 1 0 1 Function SRAM/ROM (Default) (Reserved) (Reserved) SDRAM SDRAM is set only in block address are 1. (3) Data bus width specification The data bus width is set for every block address area. The bus size is set by the BnBUS1 and BnBUS0 bits of the control register (BnCSH) as follows. BnBUS Bit (BnCSH register) BnBUS1 0 0 1 1 BnBUS0 0 1 0 1 Function 8-bit bus mode (Default) 16-bit bus mode 32-bit bus mode (Reserved) This way of changing the data bus size depending on the address being accessed is called "dynamic bus sizing". The part where the data is output to is depended on the data size, the bus width and the start address. Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus width are put in consecutive address, do not execute a access to both memories with one command. 92C820-101 2007-02-16 TMP92C820 Operand Data Size (Bit) Operand Start Address 4n + 0 4n + 1 Memory Data Size (Bit) 8/16/32 8 16/32 8/16 32 8 16 32 8 16/32 8 16 32 8 16 32 8 16 32 CPU Address 4n + 0 4n + 1 4n + 1 4n + 2 4n + 2 4n + 3 4n + 3 4n + 3 (1) 4n + 0 (2) 4n + 1 4n + 0 (1) 4n + 1 (2) 4n + 2 (1) 4n + 1 (2) 4n + 2 4n + 1 (1) 4n + 2 (2) 4n + 1 4n + 2 4n + 2 (1) 4n + 3 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (1) 4n + 0 (2) 4n + 1 (3) 4n + 2 (4) 4n + 3 (1) 4n + 0 (2) 4n + 2 4n + 0 (1) 4n + 0 (2) 4n + 1 (3) 4n + 2 (4) 4n + 3 (1) 4n + 1 (2) 4n + 2 (3) 4n + 4 (1) 4n + 1 (2) 4n + 4 (1) 4n + 2 (2) 4n + 3 (3) 4n + 4 (4) 4n + 5 (1) 4n + 2 (2) 4n + 4 (1) 4n + 2 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (3) 4n + 5 (4) 4n + 6 (1) 4n + 3 (2) 4n + 4 (3) 4n + 6 (1) 4n + 3 (2) 4n + 4 D32 to D24 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b31 to b24 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b23 to b16 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx CPU Data D23 to D16 xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b23 to b16 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b31 to b24 D15 to D8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 b15 to b8 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx xxxxx b23 to b16 D7 to D0 b7 to b0 b7 to b0 xxxxx b7 to b0 xxxxx b7 to b0 xxxxx xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 xxxxx b7 to b0 b15 to b8 b7 to b0 xxxxx b7 to b0 b15 to b8 xxxxx b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 xxxxx b31 to b24 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 xxxxx b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 xxxxx b15 to b8 8 4n + 2 4n + 3 4n + 0 4n + 1 16 4n + 2 4n + 3 4n + 0 8 16 32 8 4n + 1 16 32 32 4n + 2 8 16 32 4n + 3 8 16 32 xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains to non active. 92C820-102 2007-02-16 TMP92C820 (4) Wait control The external bus cycle completes a wait of two states at least (100 ns at 20 MHz). Setting the BnWW2 to BnWW0 and BnWR2 to BnWR0 of the control register (BnCSL) specifies the number of waits in the read cycle and the write cycle. BnWW is set with the same method as BnWR. BnWW/BnWR Bit (BnCSL register) BnWW2 BnWR2 0 0 1 1 1 0 BnWW1 BnWR1 0 1 0 1 1 1 Others BnWW0 BnWR0 1 0 1 0 1 1 Function 2states (0 waits) access fixed mode 3states (1 wait) access fixed mode (Default) 4states (2 waits) access fixed mode 5states (3 waits) access fixed mode 6states (4 waits) access fixed mode WAIT pin input mode (Reserved) Note: When SDRAM is specified as a connecting memory, setting should be 4 states (2 waits) in RD cycle and 3 states (1 wait) in WR cycle. (i) Waits number fixed mode The bus cycle is completed with the set states. The number of states is selected from 2 states (0 waits) to 5 states (3 waits). (ii) WAIT pin input mode This mode samples the WAIT input pins. It continuously samples the WAIT pin state and inserts a wait if the pin is active. The bus cycle is minimum 2 states. The bus cycle is completed when the wait signal is non active ("High" level) at 2 states. The bus cycle extends if the wait signal is active at 2 states and more. (5) Insert recovery cycle If a lot of connected pertain ROM and etc. (Much data output floating time (tDF)), each other's data-bus-output-recovery-time is trouble. However, by setting BnREC of control register (BnCSH), can insert dummy cycle of 1 state just before first bus cycle of starting access another block address. BnREC Bit (BnCSH register) 0 1 No dummy cycle is inserted (Default). Dummy cycle is inserted. Note: When use MMU, built-in RAM type LCDD, this function cannot use. 92C820-103 2007-02-16 TMP92C820 * When not inserting a dummy cycle (0 waits) SDCLK Address CSm CSn RD * When inserting a dummy cycle (0 waits) Dummy SDCLK Address CSm CSn RD (6) Basic bus timing * External read/write bus cycle (0 waits) SDCLK (20 MHz) CS T1 T2 Address RD Read D31 to D0 WRxx Input Write Output D31 to D0 * External read/write bus cycle (1 wait) SDCLK (20 MHz) CS T1 TW T2 Address RD Read D31 to D0 WRxx Input Write D31 to D0 Output 92C820-104 2007-02-16 TMP92C820 * External read/write bus cycle (0 waits at WAIT pin input mode) SDCLK (20 MHz) CS T1 T2 Address RD Read D31 to D0 WRxx Input Write D31 to D0 WAIT Output Sampling * External read/write bus cycle (n waits at WAIT pin input mode) SDCLK (20 MHz) CS T1 TW T2 Address RD Read D31 to D0 WRxx Input W D31 to D0 WAIT Output Sampling Sampling 92C820-105 2007-02-16 TMP92C820 * Example of WAIT input cycle (5 waits) FF0 D CK RES Q FF1 D CK RES Q FF2 D CK RES Q FF3 D CK RES Q FF4 D CK RES Q WAIT SDCLK CSn RD WR SDCLK (20 MHz) CSn 1 2 3 4 5 6 7 RD FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q WAIT 92C820-106 2007-02-16 TMP92C820 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers TMP92C820 supports ROM access of the page mode. The ROM access of the page mode is specified only in the block address area 2. ROM page mode is set by the page ROM control register (PMEMCR). Setting OPGE bit of the PMEMCR register to "1" sets the memory access of the block address area to ROM page mode access. The number of read cycles is set by the OPWR1 and OPWR0 bits of the PMEMCR register. OPWR1/OPWR0 Bit (PMEMCR register) OPWR1 0 0 1 1 OPWR0 0 1 0 1 Number of Cycle in a Page 1 state (n-1-1-1 mode) (n 2) 2 state (n-2-2-2 mode) (n 3) 3 state (n-3-3-3 mode) (n 4) (Reserved) Note: Set the number of waits "n" to the control register (BnCSL) in each block address area. The page size (the number of bytes) of ROM in the CPU size is set to the PR1 and 0 bit of the PMCME register. When data is read out until a border of the set page, the controller completes the page reading operation. The start data of the next page is read in the normal cycle. The following data is set to page read again. PR1/PR0 Bit (PMEMCR register) PR1 0 0 1 1 PR0 0 1 0 1 64 bytes 32 bytes ROM Page Size 16 bytes (Default) 8 bytes (2) Signal timing pulse SDCLK tCYC A0~A23 CS2 +0 +1 +2 +3 tAD3 RD tAD2 tAD2 tAD2 tHA tRD3 D0~D31 Data input tHA Data input tHA Data input tHA Data input tHR 92C820-107 2007-02-16 TMP92C820 3.6.5 List of Registers The memory control registers and the settings are described as follows. For the addresses of the registers, see Section 5 "Table of Special Function Registers (SFRs)". (1) Control registers The control register is a pair of BnCSL and BnCSH. (n is a number of the block address area.) BnCSL has the same configuration regardless of the block address areas. In BnCSH, only B2CSH which is corresponded to the block address area 2 has a different configuration from the others. BnCSL 7 Bit symbol Read/Write After reset 0 6 BnWW2 5 BnWW1 W 1 4 BnWW0 0 3 2 BnWR2 0 1 BnWR1 W 1 0 BnWR0 0 BnWW<2:0> Specifies the number of write waits. 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 111 = 6 states (4 waits) access Others = (Reserved) BnWR<2:0> Specifies the number of read waits. 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 111 = 6 states (4 waits) access Others = (Reserved) 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode B2CSH 7 Bit symbol Read/Write After reset B2E: Enable bit 0 = No chip select signal output. 1 = Chip select signal output (Default). Note: After reset release, only the enable bit B2E of B2CS register is valid ("1"). B2M: Block address area specification 0 = Sets the block address area of CS2 to addresses 000000H to FFFFFFH (Default). 1 = Sets the block address area of CS2 to programmable. Note: After reset release, the block address area 2 is set to addresses 000000H to FFFFFFH. 1 B2E W 0 0 0 6 B2M 5 4 B2REC 3 B2OM1 2 B2OM0 W 0 1 B2BUS1 0/1 0 B2BUS0 0/1 92C820-108 2007-02-16 TMP92C820 B2REC: Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default). 1 = Insert a dummy cycle. Note: When using MMU, LCD of built-in RAM type, this function cannot use. B2OM<1:0> 00 = SRAM or ROM (Default) Others = (Reserved) B2BUS<1:0> Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = (Reserved) Note: The value of B2BUS bit is set according to the state of AM<1:0> pin after reset release. BnCSH (n = 0, 1, 3) 7 Bit symbol Read/Write After reset BnE: Enable bit 0 = No chip select signal output (Default). 1 = Chip select signal output. Note: After reset release, only the enable bit B2E of B2CS register is valid ("1"). BnREC: Sets the dummy cycle for data output. 0 = Not insert a dummy cycle (Default). 1 = Insert a dummy cycle. Note: When using MMU, LCD of built-in RAM type, this function cannot use. BnOM<1:0> 00 = SRAM or ROM (Default) 01 = (Reserved) 10 = (Reserved) 11 = SDRAM Note: SDRAM is set only by B1CSH. BnBUS<1:0> Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = (Reserved) BnE W 0 0 0 6 5 4 BnREC 3 BnOM1 2 BnOM0 W 0 1 BnBUS1 0 0 BnBUS0 0 92C820-109 2007-02-16 TMP92C820 BEXCSL 7 Bit symbol Read/Write After reset 0 6 BEXWW2 5 BEXWW1 W 1 4 BEXWW0 0 3 2 BEXWR2 0 1 BEXWR1 W 1 0 BEXWR0 0 BEXWW<2:0> specifies the number of write waits. 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 111 = 6 states (4 waits) access Others = (Reserved) BEXWR<2:0> Specifies the number of read waits. 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 111 = 6 states (4 waits) access Others = (Reserved) 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode 010 = 3 states (1 wait) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode BEXCSH 7 Bit symbol Read/Write After reset BEXOM<1:0> 00 = SRAM or ROM (Default) 01 = (Reserved) 10 = (Reserved) 11 = (Reserved) BEXBUS<1:0> Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = (Reserved) 0 0 6 5 4 3 BEXOM1 2 BEXOM0 W 1 BEXBUS1 0 0 BEXBUS0 0 92C820-110 2007-02-16 TMP92C820 (2) Block address register A start address and an address area of the block address are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The memory start address register sets all start address similarly regardless of the block address areas. The bit to be set by the memory address mask register is depended on the block address area. MSARn (n = 0 to 3) 7 Bit symbol Read/Write After reset 1 1 1 1 MnS23 6 MnS22 5 MnS21 4 MnS20 R/W 3 MnS19 1 2 MnS18 1 1 MnS17 1 0 MnS16 1 MnS<23:16> Sets a start address. Sets the start address of the block address areas. The bits are corresponding to the address A23 to A16. MAMR0 7 Bit symbol Read/Write After reset M0V<20:8> Enables or masks comparison of the addresses. M0V20 to M0V8 are corresponding to addresses A20 to A8. The bits of M0V14 to M0V9 are corresponding to address A14 to A9 by 1 bit. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. 1 1 1 1 M0V20 6 M0V19 5 M0V18 4 M0V17 R/W 3 M0V16 2 M0V15 1 M0V14 to M0V9 1 0 M0V8 1 1 1 MAMR1 7 Bit symbol Read/Write After reset M1V<21:8> Enables or masks comparison of the addresses. M1V21 to M1V8 are corresponding to addresses A21 to A8. The bits of M1V15 to M1V9 are corresponding to address A15 to A9 by 1 bit. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. 1 1 1 1 M1V21 6 M1V20 5 M1V19 4 M1V18 R/W 3 M1V17 2 M1V16 1 M1V15 to M1V9 1 0 M1V8 1 1 1 MAMRn (n = 2 to 3) 7 Bit symbol Read/Write After reset MnV<22:15> Enables or masks comparison of the addresses. MnV22 to MnV15 are corresponding to addresses A22 to A15. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. 1 1 1 1 MnV22 6 MnV21 5 MnV20 4 MnV19 R/W 3 MnV18 1 2 MnV17 1 1 MnV16 1 0 MnV15 1 After a reset, MASR0 to MASR3 and MAMR0 to MAMR3 are set to "FFH". B0CSH 92C820-111 2007-02-16 TMP92C820 (3) Page ROM control register (PMEMCR) The page ROM control register sets page ROM accessing. ROM page accessing is executed only in block address area 2. PMEMCR 7 Bit symbol Read/Write After reset OPGE enable bit 0 = No ROM page mode accessing (Default) 1 = ROM page mode accessing OPWR<1:0> Specifies the number of waits. 00 = 1 state (n-1-1-1 mode) (n 2) (Default) 01 = 2 states (n-2-2-2 mode) (n 3) 10 = 3 states (n-3-3-3 mode) (n 4) 11 = (Reserved) Note: Set the number of waits "n" to the control register (BnCSL) in each block address area. PR<1:0> ROM page size 00 = 64 bytes 01 = 32 bytes 10 = 16 bytes (Default) 11 = 8 bytes 0 0 6 5 4 OPGE 3 OPWR1 2 OPWR0 R/W 0 1 PR1 1 0 PR0 0 92C820-112 2007-02-16 TMP92C820 Table 3.6.1 Control Register 7 B0CSL (0140H) B0CSH (0141H) MAMR0 (0142H) MSAR0 (0143H) B1CSL (0144H) B1CSH (0145H) MAMR1 (0146H) MSAR1 (0147H) B2CSL (0148H) B2CSH (0149H) MAMR2 (014AH) MSAR2 (014BH) B3CSL (014CH) B3CSH (014DH) MAMR3 (014EH) MSAR3 (014FH) BEXCSH (0159H) BEXCSL (0158H) PMEMCR (0166H) Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset Bit symbol Read/Write After reset 6 B0WW2 0 - 0 (Note) M0V19 1 M0S22 1 B1WW2 0 - 0 (Note) M1V20 1 M1S22 1 B2WW2 0 B2M 0 M2V21 1 M2S22 1 B3WW2 0 - 0 (Note) M3V21 1 M3S22 1 5 B0WW1 W 1 - 0 (Note) M0V18 1 M0S21 1 B1WW1 W 1 - 0 (Note) M1V19 1 M1S21 1 B2WW1 W 1 - 0 (Note) M2V20 1 M2S21 1 B3WW1 W 1 - 0 (Note) M3V20 1 M3S21 1 4 B0WW0 0 B0REC W 0 M0V17 R/W 1 M0S20 R/W 1 B1WW0 0 B1REC W 0 M1V18 R/W 1 M1S20 R/W 1 B2WW0 0 B2REC W 0 M2V19 R/W 1 M2S20 R/W 1 B3WW0 0 B3REC W 0 M3V19 R/W 1 M3S20 R/W 1 3 2 B0WR2 0 B0OM0 0 M0V15 1 M0S18 1 B1WR2 0 B1OM0 0 M1V16 1 M1S18 1 B2WR2 0 B2OM0 0 M2V17 1 M2S18 1 B3WR2 0 B3OM0 0 M3V17 1 M3S18 1 BEXOM0 W 0 BEXWR2 0 OPWR0 R/W 0 1 B0WR1 W 1 B0BUS1 0/1 M0V14-V9 1 M0S17 1 B1WR1 W 1 B1BUS1 0/1 M1V15-V9 1 M1S17 1 B2WR1 W 1 B2BUS1 0/1 M2V16 1 M2S17 1 B3WR1 W 1 B3BUS1 0/1 M3V16 1 M3S17 1 BEXBUS1 0 BEXWR1 W 1 PR1 1 0 B0WR0 0 B0BUS0 0/1 M0V8 1 M0S16 1 B1WR0 0 B1BUS0 0/1 M1V8 1 M1S16 1 B2WR0 0 B2BUS0 0/1 M2V15 1 M2S16 1 B3WR0 0 B3BUS0 0/1 M3V15 1 M3S16 1 BEXBUS0 0 BEXWR0 0 PR0 0 B0E 0 M0V20 1 M0S23 1 B0OM1 0 M0V16 1 M0S19 1 B1E 0 M1V21 1 M1S23 1 B1OM1 0 M1V17 1 M1S19 1 B2E 1 M2V22 1 M2S23 1 B2OM1 0 M2V18 1 M2S19 1 B3E 0 M3V22 1 M3S23 1 B3OM1 0 M3V18 1 M3S19 1 BEXOM1 0 BEXWW2 0 BEXWW1 W 1 BEXWW0 0 OPGE 0 OPWR1 0 Note: Always write "0". 92C820-113 2007-02-16 TMP92C820 3.6.6 Cautions (1) Note on timing between CS and RD If the parasitic capacitance of the read signal (Output enable signal) is greater than that of the chip select signal, it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.6.1 0H SDCLK (20 MHz) Address MEMORY 1CS MEMORY 2CS RD (a) Figure 3.6.1 Read Signal Delay Read Cycle Example: When using an externally connected flash EEPROM which users JEDEC standard commands, note that the toggle bit may not be read out correctly. If the read signal in the cycle immediately preceding the access to the flash EEPROM does not go high in time, as shown in Figure 3.6.2 an unintended read cycle like the one shown in (b) may occur. 1H Memory access SDCLK (20 MHz) Address Flash EEPROM Chip select Read Toggle bit (b) Toggle bit RD cycle 1 Figure 3.6.2 Flash EEPROM Toggle Bit Read Cycle When the toggle bit reverse with this unexpected read cycle, TMP92C820 always reads same value of the toggle bit, and cannot read the toggle bit correctly. To avoid this phenomena, the data polling control recommended. 92C820-114 2007-02-16 TMP92C820 (2) The cautions at the time of the functional change of a CSn . A chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control register are initialized by the reset action, and an object terminal is initialized by the port output ("1" or "0") by it. Functional change Although an object terminal is changed from a port to a chip select signal output by setting up a function control register (PnFC register), the short pulse for several ns may be outputted to the changing timing. Although it does not become especially a problem when using the usual memory, it may become a problem when using a special memory. * XX is a function register address.(When an output port is initialized by "0") A port is set as CSn . Internal Signal Internal address bus Function control signal Output port External Signal Pxx A23 to A0 n n+2 Output pulse tAD3 CSn n XX n+2 The measure by software The countermeasures in S/W for avoiding this phenomenon are explained. Since CS signal decodes the address of the access area and is generated, an unnecessary pulse is outputted by access to the object CS area immediately after setting it as a CSn function. Then, if internal area is accessed also immediately after setting a port as CS function, an unnecessary pulse will not output. 1. The ban on interruption under functional change (DI command) 2. 3. A dummy command is added in order to carry out continuous internal access. (Access to a functional change register is corresponded by 16-bit command. (LDW command)) A port is set as CSn . Internal Internal address bus Function control signal Output port External signal Pxx A23 to A0 n n+2 CSn Dummy access n+2 signal XX XX+1 92C820-115 2007-02-16 TMP92C820 3.7 8-Bit Timers (TMRA) The TMP92C820 features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. * * * * 0H 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) 1H Figure 3.7.1 to Figure 3.7.2 Show block diagrams for TMRA01 and TMRA23. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five controls SFR (Special function register). Each of the two modules (TMRA01 and TMRA23) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter are as follows. 3.7.1 3.7.2 3.7.3 3.7.4 Block Diagrams Operation of Each Circuit SFRs Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM output mode (5) Mode setting Table 3.7.1 Registers and Pins for Each Module Module TMRA01 TA0IN Input pin for external clock (shared with PC0) Output pin for timer flip-flop Timer run register SFR (Address) Timer register Timer mode register Timer flip-flop control register TA1OUT (shared with PC1) TA01RUN (1100H) TA0REG (1102H) TA1REG (1103H) TA01MOD (1104H) TA1FFCR (1105H) No TA3OUT (Shared with PC5) TA23RUN (1108H) TA2REG (110AH) TA3REG (110BH) TA23MOD (110CH) TA3FFCR (110DH) TMRA23 External pin 92C820-116 2007-02-16 3.7.1 Prescaler Run/clear TA01RUN Prescaler clock: T0 T16 Timer flip-flop TA1FF TA01RUN overflow n 2 T256 4 8 16 32 64 128 256 512 T1 T4 Block Diagrams Timer flip-flop output: TA1OUT Selector T1 T16 T256 TA01MOD External input clock: TA0IN T1 T4 T16 Figure 3.7.1 TMRA01 Block Diagram TA01MOD 92C820-117 8-bit comparator (CP0) TA01MOD TA0TRG TA01MOD 8-bit comparator (CP1) Match detect 8-bit timer register TA1REG TA01RUN TMP92C820 2007-02-16 Internal data bus TMRA0 interrupt output: INTTA0 Internal data bus TMRA0 match output: TA0TRG TMRA1 interrupt output: INTTA1 Prescaler 8 T16 Timer flip-flop TA3FF TA23RUN n Prescaler clock: T0 16 32 64 128 256 512 T256 TA23RUN 2 4 Run/clear T1 T4 Timer flip-flop output: TA3OUT (Supply to LCDC) Selector T1 T16 T256 T1 T4 T16 Figure 3.7.2 TMRA23 Block Diagram 92C820-118 8-bit comparator (CP2) TA23MOD TA23MOD 8-bit comparator register (CP3) Match detect 8-bit timer register TA3REG TA23RUN TMP92C820 2007-02-16 Internal data bus TMRA2 match output: TA2TRG TMRA3 interrupt output: INTTA3 TMP92C820 3.7.2 Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The clock T0 is divided into 8 by the CPU clock fSYS and input to this prescaler. The prescaler operation can be controlled using TA01RUN 2H Table 3.7.2 Prescaler Output Clock Resolution Clock gear selection SYSCR1 - T1(1/2) fs/16 fc/16 fc/32 fc/64 fc/128 fc/256 Timer counter input clock TMRA prescaler TAxMOD fs/64 fc/64 fc/128 fc/256 fc/512 fc/1024 fs/256 fc/256 fc/512 fc/1024 fc/2048 fc/4096 fs/4096 fc/4096 fc/8192 fc/16384 fc/32768 fc/65536 (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks T1, T4 or T16. The clock setting is specified by the value set in TA01MOD 92C820-119 2007-02-16 TMP92C820 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN 3H Timer registers 0 (TA0REG) B Shift trigger Register buffers 0 Selector S A Write to TA0REG Matching detection in PPG cycle n 2 overflow of PWM Write Internal data bus TA01RUN Figure 3.7.3 Configuration of TA0REG Note: The same memory address is allocated to the timer register and the register buffer. When All these registers are write-only and cannot be read. 92C820-120 2007-02-16 TMP92C820 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained below. If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up-counter value, the timer flip-flop may output an unexpected value. For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (fSYS x 6) before the next overflow occurs by using an overflow interrupt. When using PPG mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt. Example when using PWM mode Match between TA0REG and up-counter 2 overflow interrupt (INTTA0) TA1OUT tPWM (PWM cycle) n Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt 92C820-121 2007-02-16 TMP92C820 3.7.3 SFRs TMRA01 Run Register 7 TA01RUN (1100H) Bit symbol Read/Write After reset Function TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 6 5 4 3 I2TA01 R/W 0 IDLE2 0: Stop 1: Operate 2 TA01PRUN 0 TMRA01 prescaler 1 TA1RUN R/W 0 UP counter (UC1) 0 TA0RUN 0 UP counter (UC0) 0: Stop and clear 1: Run (Count up) Timer run/stop control 0 1 0 1 Stop and clear Run (Count up) Disable Enable TA0REG double buffer control Note: The values of bits 4 to 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 TA23RUN (1108H) Bit symbol Read/Write After reset Function TA2RDE R/W 0 Double buffer 0: Disable 1: Enable 6 5 4 3 I2TA23 R/W 0 IDLE2 0: Stop 1: Operate 2 TA23PRUN 1 TA3RUN R/W 0 UP counter (UC3) 0 TA2RUN 0 UP counter (UC4) 0 TMRA23 prescaler 0: Stop and clear 1: Run (Count up) Timer run/stop control 0 1 0 1 Stop and clear Run (Count up) Disable Enable TA2REG double buffer control Note: The values of bits 4 to 6 of TA23RUN are undefined when read. Figure 3.7.4 TMRA Registers (1) 92C820-122 2007-02-16 TMP92C820 TMRA01 Mode Register 7 TA01MOD Bit symbol (1104H) Read/Write After reset Function TA01M1 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 6 TA01M0 0 5 PWM01 0 PWM cycle 00: Reserved 01: 2 6 7 8 4 PWM00 0 R/W 3 TA1CLK1 0 00: TA0TRG 01: T1 10: T16 11: T256 2 TA1CLK0 0 1 TA0CLK1 0 0 TA0CLK0 0 Source clock for TMRA1 Source clock for TMRA0 00: TA0IN pin (Note) 01: T1 10: T4 11: T16 10: 2 11: 2 TMRA0 source clock selection 00 01 10 11 TA0IN (External input) T1 T4 T16 TA01MOD Overflow output from TMRA0 TMRA1 source clock selection TA01MOD Comparator output from TMRA0 T1 T16 T256 Reserved 2 x Source clock 6 7 8 (16-bit timer mode) PWM cycle selection 2 x Source clock 2 x Source clock Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA0) + 8-bit timer (TMRA1) TMRA01 operation mode selection Note: When set TA0IN pin, must set TA01MOD after set port C. Figure 3.7.5 TMRA Registers (2) 92C820-123 2007-02-16 TMP92C820 TMRA23 Mode Register 7 TA23MOD Bit symbol (110CH) Read/Write After reset Function TA23M1 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 6 TA23M0 0 5 PWM21 0 PWM cycle 00: Reserved 01: 2 6 7 8 4 PWM20 0 R/W 3 TA3CLK1 0 00: TA2TRG 01: T1 10: T16 11: T256 2 TA3CLK0 0 1 TA2CLK1 0 00: Reserved 01: T1 10: T4 11: T16 0 TA2CLK0 0 TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 10: 2 11: 2 TMRA2 source clock selection 00 01 10 11 Do not set T1 T4 T16 TA23MOD Overflow output from TMRA2 TMRA3 source clock selection TA23MOD Comparator output from TMRA2 T1 T16 T256 Reserved 2 x Source clock 6 7 8 (16-bit timer mode) PWM cycle selection 2 x Source clock 2 x Source clock Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA2) + 8-bit timer (TMRA3) TMRA23 operation mode selection Figure 3.7.6 TMRA Registers (3) 92C820-124 2007-02-16 TMP92C820 TMRA1 Flip-Flop Control Register 7 TA1FFCR (1105H) Bit symbol Read/Write 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don't care 6 5 4 3 TA1FFC1 R/W 2 TA1FFC0 1 1 TA1FFIE R/W 0 TA1FF control for inversion 0: Disable 1: Enable 0 TA1FFIS 0 TA1FF1 inversion select 0: TMRA0 1: TMRA1 Read-modify After reset -write instructions Function are prohibited. Inverse signal for timer flop-flop 1 (TA1FF) (Don't care except in 8-bit timer mode) 0 1 0 1 00 01 10 11 Note: The values of bits 4 to 7 of TA1FFCR are undefined when read. Inversion by TMRA0 Inversion by TMRA1 Disabled Enabled Inverts the value of TA1FF Sets TA1FF to "1" Clears TA1FF to "0" Don't care Inversion of TA1FF Control of TA1FF Figure 3.7.7 TMRA Registers (4) 92C820-125 2007-02-16 TMP92C820 TMRA3 Flip-Flop Control Register 7 TA3FFCR (110DH) Bit symbol Read/Write 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don't care 6 5 4 3 TA3FFC1 R/W 2 TA3FFC0 1 1 TA3FFIE R/W 0 TA3FF control for inversion 0: Disable 1: Enable 0 TA3FFIS 0 TA3FF inversion select 0: TMRA2 1: TMRA3 Read-modify After reset -write instructions Function are prohibited. Inverse signal for timer flip-flop 3 (TA3FF) (Don't care except in 8-bit timer mode) 0 1 0 1 00 01 10 11 Note: The values of bits 4 to 7 of TA3FFCR are undefined when read. Inversion by TMRA2 Inversion by TMRA3 Disabled Enabled Inverts the value of TA3FF Sets TA3FF to "1" Clears TA3FF to "0" Don't care Inversion of TA3FF Control of TA3FF Figure 3.7.8 TMRA Register 92C820-126 2007-02-16 TMP92C820 TMRA Register (TA0REG to TA3REG) Symbol TA0REG Address 1102H 7 6 5 4 - W Undefined - 3 2 1 0 TA1REG 1103H W Undefined - TA2REG 110AH W Undefined - TA3REG 110BH W Undefined Note: Read-modify-write instruction is prohibited for above registers. Figure 3.7.9 Register for 8-Bit Timers 92C820-127 2007-02-16 TMP92C820 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both timer 0 and timer 1 can be used independently as 8-bit interval timers. 1. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using timer 1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 40 s at fC = 40 MHz, set each register as follows: MSB 7 TA01RUN TA01MOD TA1REG INTETA01 TA01RUN 0 0 6 0 1 5 - 1 0 4 - 0 1 3 0 0 - 2 - 1 1 - 1 1 0 - 0 - 1 0 - - 0 - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (=(16/fc)s at fC = 40 MHz) as the input clock. Set TA1REG to 40 s / T1 = 100 = 64H Enable INTTA1 and set it to level 5. Start TMRA1 counting. - X X X - LSB X 1 - X X X - X: Don't care, -: No change Select the input clock using Table 3.7.3 4H Table 3.7.3 Selecting Interrupt Interval and the Input Clock Using 8-Bit Timer Input Clock T1 (8/fSYS) T4 (32/fSYS) T16 (128/fSYS) T256 (2048/fSYS) Interrupt Interval (at fSYS = 20 MHz) 0.4 s to 102.4 s 1.6 s to 409.6 s 6.4 s to 1.638 ms 102.4 s to 26.21 ms Resolution 0.4 s 1.6 s 6.4 s 102.4 s Note: The input clocks for TMRA0 and TMRA1 differ as follows: TMRA0: Uses TMRA0 input (TA0IN) and can be selected from T1, T4, or T16 TMRA1: Match output of TMRA0 (TA0TRG) and can be selected from T1, T16, T256 92C820-128 2007-02-16 TMP92C820 2. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4 s square wave pulse from the TA1OUT pin at fC = 40 MHz, use the following procedure to make the appropriate register settings. This example uses timer 1; however, either timer 0 or timer 1 may be used. 7 TA01RUN TA01MOD TA1REG TA1FFCR PCCR PCFC TA01RUN 0 0 6 0 0 5 - 0 4 - 0 3 0 0 2 - 1 0 0 1 0 - 1 1 0 - - 1 1 - - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (=(16/fc)s at fC = 40 MHz) as the input clock. Set the timer register to 2.4 s / T1 / 2 = 3 Clear TA1FF to 0 and set it to invert on the match detect signal from timer 1. Set PC1 to function as the TA1OUT pin. Start TMRA1 counting. - X X X - X X X X 1 X - X - -X-X1 -X-X1 1 1 - X X X - X: Don't care, -: No change T1 TA01RUN Figure 3.7.10 Square Wave Output Timing Chart (50% duty) 92C820-129 2007-02-16 TMP92C820 3. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (Timer 0 match) Timer 0 up counter (when TA0REG = 5) Timer 1 up counter (when TA1REG = 2) Timer 1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.11 TMRA1 Count Up on Signal from TMRA0 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD 5H To set the timer interrupt interval, set the lower eight bits in timer register TA0REG and the upper eight bits in TA1REG. Be sure to set TA0REG first (as entering data in TA0REG temporarily disables the compare, while entering data in TA1REG starts the compare). Example: To generate an INTTA1 interrupt every 0.4 s at fC = 40 MHz, set the timer registers TA0REG and TA1REG as follows: If T16 (=(256/fc)s at fSYS = 20 MHz) is used as the input clock for counting, set the following value in the registers: 0.4 s /=(256/fc)s = 62500 = F424H; e.g., set TA1REG to F4H and TA0REG to 24H. 92C820-130 2007-02-16 TMP92C820 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparator TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1, UC0) TMRA0 comparator match detect signal TMRA1 comparator match detect signal Interrupt INTTA0 Interrupt INTTA1 Timer output TA1OUT Inversion 0080H 0180H 0280H 0380H 0480H 0080H Figure 3.7.12 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active low or active high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin (which can also be used as PC1). tH Figure 3.7.13 8-Bit PPG Output Waveforms 92C820-131 2007-02-16 TMP92C820 In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN 6H TA01RUN TA1OUT TA1FFCR TA1FF Inversion INTTA0 Comparator Comparator INTTA1 Selector TA0REG Shift trigger TA0REG-WR TA01RUN Internal data bus Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low duty waves (when duty is varied). Match with TA0REG and up counter (Up counter = Q1) Match with TA1REG TA0REG (Value to be compared) Register buffer Shift from register buffer Q1 Q2 Q2 Q3 TA0REG (Register buffer) write (Up countner = Q2) Figure 3.7.15 Operation of Register Buffer 92C820-132 2007-02-16 TMP92C820 Example: To generate 1/4 duty 62.5 kHz pulses (at fC = 40 MHz): 16 s Calculate the value which should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 s T1 (=(16/fc)) (at fC = 40 MHz); 16 s /(16/fc)s = 40 Therefore set TA1REG to 40 (28H) The duty is to be set to 1/4: t x 1/4 = 16 s x 1/4 = 4 s 4 s / (16/fc)s = 10 Therefore, set TA0REG = 10 = 0AH. 7 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR PCCR PCFC TA01RUN 1 0 0 6 0 0 0 5 - 0 1 4 - 0 0 3 - 1 1 2 0 - 0 0 1 1 0 0 1 0 1 0 0 1 0 0 - - - 1 Stop TMRA0 and TMRA1 and clear it to "0". Set the 8-bit PPG mode, and select T1 as input clock. Write 0AH Write 28H Set TA1FF, enabling both inversion and the double buffer. 10 generates a negative logic pulse. Set PC1 as the TA1OUT pin. Start TMRA0 and TMRA1 counting. 0 X X X - X X X X 0 X - X - -X-X1 -X-X1 1 1 1 X X X - X: Don't care, -: No change 92C820-133 2007-02-16 TMP92C820 (4) 8-bit PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as PC1). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD TA0REG and UC0 match 2 overflow (INTTA0 interrupt) n TA1OUT tPWM (PWM cycle) Figure 3.7.16 8-Bit PWM Waveforms Figure 3.7.17 shows a block diagram representing this mode. 7H TA01RUN TA1OUT Selector Clear TAFF1 Invert TA1FFCR TA01MOD 2 overflow control Overflow n TA01MOD Comparator INTTA0 TA0REG Selector TA0REG-WR TA01RUN Internal data bus Figure 3.7.17 Block Diagram of 8-Bit PWM Mode 92C820-134 2007-02-16 TMP92C820 In this mode the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q1 2 overflow Shift into TA0REG TA0REG (Value to be compared) Register buffer Q1 Q2 Q2 Q3 TA0REG (Register buffer) write n Up counter = Q2 Figure 3.7.18 Register Buffer Operation Example: To output the following PWM waves on the TA1OUT pin at fC = 40 MHz: 36.0 s 51.2 s To achieve a 51.2 s PWM cycle by setting T1 to 0.4 s (at fC = 40 MHz): 51.2 s / (16/fc)s = 128 n 2 = 128 Therefore n should be set to 7. Since the low-level period is 36.0 s when T1 = (16/fc) s, set the following value for TREG0: 36.0 s /(16/fc)s = 90 = 5AH MSB 7 TA01RUN TA01MOD TA0REG TA1FFCR PCCR PCFC TA01RUN 1 0 6 1 1 5 1 0 4 0 1 3 - 1 2 - - 0 0 1 - 0 1 1 0 0 1 0 - - - 1 Stop TMRA0 and clear it to 0. Select 8-bit PWM mode (Cycle: 2 ) and select T1 as the input clock. 7 LSB - X X X - Write 5AH. Clear TA1FF to 0, enable the inversion and double buffer. Set PC1 and the TA1OUT pin. Start TMRA0 counting. X X X X 1 X - X - -X-X1 -X-X1 1 - 1 X X X - X: Don't care, -: No change 92C820-135 2007-02-16 TMP92C820 Table 3.7.4 PWM Cycle PWM cycle Clock gear SYSCR1 TAxxMOD 4096/fs 4096/fc 8192/fc 16384/fc 32768/fc 65536/fc 6 2 (x128) TAxxMOD 2048/fs 2048/fc 4096/fc 8192/fc 16384/fc 32768/fc 7 2 (x256) TAxxMOD 4096/fs 4096/fc 8192/fc 16384/fc 32768/fc 65536/fc 8 T16(x32) 16384/fs 16384/fc 32768/fc 65536/fc 131072/fc 262144/fc T4(x8) 8192/fs 8192/fc 16384/fc 32768/fc 65536/fc 131072/fc T16(x32) 32768/fs 32768/fc 65536/fc 131072/fc 262144/fc 524288/fc T4(x8) 16384/fs 16384/fc 32768/fc 65536/fc 131072/fc 262144/fc T16(x32) 65536/fs 65536/fc 131072/fc 262144/fc 524288/fc 1048576/fc - 000(x1) 001(x2) 010(x4) 011(x8) 100(x16) 1(fs) 1024/fs 1024/fc 0(fc) x8 2048/fc 4096/fc 8192/fc 16384/fc (5) Mode setting Table 3.7.5 shows the SFR settings for each mode. 8H Table 3.7.5 Timer Mode Setting Registers Register Name Lower timer match, T1, T16, T256 (00, 01, 10, 11) - TA1FFCR 0: Lower timer output 1: Upper timer output Lower Timer Input Clock External clock, T1, T4, T16 (00, 01, 10, 11) External clock, 8-bit timer x 2 channels 00 - 16-bit timer mode 01 - T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) - - 8-bit PPG x 1 channel 10 - - - 8-bit PWM x 1 channel 8-bit timer x 1 channel 11 2,2,2 (01, 10, 11) - 6 7 8 - T1, T16, T256 (01, 10, 11) - 11 Output disabled -: Don't care 92C820-136 2007-02-16 TMP92C820 3.8 External Memory Extension Function (MMU) This is MMU function which can expand program/data area to 136 Mbytes by having 4 local area. Address pins to external memory are 2 extended address bus pins (EA24, EA25) and 8 extended chip select pins ( CS2A to CS2G and CSEXA ) in addition to 24 address bus pins (A0 to A23) which are common specification of TLCS-900/H1 and 4 chip select pins ( CS0 to CS3 ) output from MEMC. The feature and the recommendation setting method of two types are shown below. In addition, AH in the table is the value which number address 23 to 16 displayed as hex. For Standard Extended Memory For Many Kinds Class Extended Memory Purpose Program ROM Item Maximum memory size Used local area, BANK number Setting MEMC Used CS pin 2 Mbytes: COMMON2 + 14 Mbytes: BANK (16 Mbytes x 1 pcs) LOCAL2 (AH = C0 to DF: 2 Mbytes x 7 BANK) Setup AH = "80 to FF" to CS2 CS2A Data ROM Maximum memory size Used local area, BANK number Setting MEMC Used CS pin 96 Mbytes (16 Mbytes x 6 pcs) LOCAL3 (AH = 80 to BF: 4 Mbytes x 24 BANK) Setup AH = "80 to FF" to CS2 CS2B , CS2C , CS2D , CS2E , CS2F , CS2G Data SDRAM* Maximum memory size Used local area, BANK number Setting MEMC Used CS pin 2 Mbytes: COMMON1 + 14 Mbytes: BANK (16 Mbytes x 1 pcs) LOCAL1 (AH = 40 to 5F: 2 Mbytes x 7 BANK) Setup AH = "40 to 7F" to CS1 CS1 Data RAM Maximum memory size Used local area, BANK number Setting MEMC Used CS pin 1 Mbyte: COMMON0 + 7 Mbytes: BANK (8 Mbytes x 1 pcs) LOCAL0 (AH = 10 to 1F: 1 Mbyte x 7 BANK) Setup AH = "00 to 1F" to CS3 CS3 Extended memory 1 Maximum memory size Used local area, BANK number Setting MEMC Used CS pin 1 Mbyte (1 Mbyte x 1 pcs) None Setup AH = "20 to 2F" to CS0 CS0 Extended memory 2 Maximum memory size Used local area, BANK number Setting MEMC Used CS pin 256 Kbytes (256 Kbytes x 1 pcs) None Setup AH = "30 to 3F" to CSEX CSEXA Extended memory 3 (Direct address assigned built-in type LCD driver) Maximum memory size Used local area, BANK number Setting MEMC Used CS pin 256 Kbytes (64 Kbytes x 4 pcs) None Setup AH = "30 to 3F" to CSEX D1BSCP, D2BLP, D3BFR, DLEBCD 512 Kbytes None Setup AH = "30 to 3F" to CSEX None Extended memory 4 Maximum memory size Used local area, BANK number Setting MEMC Used CS pin *Note: SDRAM must be mapped in LOCAL1 area. It can't use other area. 92C820-137 2007-02-16 TMP92C820 3.8.1 Recommendable Memory Map The recommendation logic address memory map at the time of variety extension memory correspondence is shown in Figure 3.8.1. And, a physical-address map is shown in Figure 3.8.2. However, when memory area is less than 16 Mbytes and is not expanded, please refer to section of MEMC. Setting of register in MMU is not necessary. Since it is being fixed, the address of a local-area cannot be changed. When SDRAM is used, must locate to LOCAL1 area. 0H 1H Address 000000H Size 1 Mbyte Memory map COMMON0 LOCAL0 0 1 2 BANK CS/WAIT CS pin 100000H 200000H 300000H 380000H 3C0000H 3D0000H 3E0000H 3F0000H 400000H 600000H CS3 3 4 5 6 7 CS0 CSEX CSEX CSEX CSEX CSEX CSEX CS3 1 Mbyte 1 Mbyte 512 Kbytes 256 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 2 Mbytes 2 Mbytes CS0 to CSEXA D1BSCP D2BLP D3BFR DLEBCD LOCAL1 COMMON1 0 1 2 3 4 5 6 7 CS1 CS1 800000H CS2B (BANK0 to BANK3) CS2C (BANK4 to BANK7) CS2D (BANK8 to BANK11) CS2E (BANK12 to BANK15) CS2F (BANK16 to BANK19) 4 Mbytes LOCAL3 0 1 2 22 23 CS2 C00000H 2 Mbytes E00000H 2 Mbytes FFFF00H FFFFFFH 256 bytes COMMON2 Vector area LOCAL2 0 1 2 3 4 5 6 7 CS2 CS2G (BANK20 to BANK23) CS2A : Internal area : Overlapped with COMMON area Figure 3.8.1 Logical Address Map 92C820-138 2007-02-16 TMP92C820 TMP92C820 LOCAL0 CS3 LOCAL1 CS1 LOCAL2 CS2A CS2B LOCAL3 CS2E for data RAM (SDRAM non support) (8 Mbytes) 000000H BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 for option program ROM (SDRAM support) (16 Mbytes) BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 for program ROM (16 Mbytes) for data ROM (16 Mbytes x 6) BANK0 BANK0 BANK1 BANK2 BANK1 BANK3 BANK4 BANK2 BANK5 BANK6 BANK3 BANK7 BANK15 BANK14 BANK13 BANK12 Internal-I/O and RAM 800000H 1000000H CS2C CS2F 000000H Reset and Interrupt vector area BANK4 BANK16 BANK5 BANK17 BANK6 BANK18 BANK7 1000000H CS2D BANK19 CS2G 000000H BANK8 BANK20 BANK9 BANK21 BANK10 : Internal area : Overlapped with COMMON area BANK11 1000000H BANK22 BANK23 Figure 3.8.2 Physical Address Map 92C820-139 2007-02-16 TMP92C820 3.8.2 Block Diagram CPU out address A23 to A8 A23 to A16 Decoder A23 to A20 LOCAL0 register LOCAL1 register LOCAL2 register LOCAL3 register L0E L1E L2E L3E EA22 to EA20 EA23 to EA21 EA23 to EA21 Selector EA26 to EA22 (To external address bus pins) Physical address VA26 to VA20 Selector Physical address WA26 to WA7 LOCAL3 area detect signal Internal data bus CPU out address A19 to A7 CPU out address A23 to A16 LOCAL3 area detect signal LOCAL3 register Decoder CS2A CS2B CS2C CS2D CS2E CS2F CS2G CSEXA Figure 3.8.3 Block Diagram of MMU 92C820-140 2007-02-16 TMP92C820 3.8.3 Control Registers LOCAL0 Register 7 LOCAL0 (01D0H) Bit symbol Read/Write After reset Function L0E R/W 0 Use BANK for LOCAL0 0: Not use 1: Use 0 6 5 4 3 2 L0EA22 1 L0EA21 R/W 0 0 L0EA20 0 Setting BANK number for LOCAL0 LOCAL1 Register 7 LOCAL1 (01D1H) Bit symbol Read/Write After reset Function L1E R/W 0 Use BANK for LOCAL1 0: Not use 1: Use 0 6 5 4 3 2 L1EA23 1 L1EA22 R/W 0 0 L1EA21 0 Setting BANK number for LOCAL1 LOCAL2 Register 7 LOCAL2 (01D2H) Bit symbol Read/Write After reset Function L2E R/W 0 Use BANK for LOCAL2 0: Disable 1: Enable 0 6 5 4 3 2 L2EA23 1 L2EA22 R/W 0 0 L2EA21 0 Setting BANK number for LOCAL2 LOCAL3 Register 7 LOCAL3 (01D3H) Bit symbol Read/Write After reset Function L3E R/W 0 Use BANK for LOCAL3 0: Disable 1: Enable 0 0 00000 to 00011 CS2B 01000 to 01011 CS2D 10000 to 10011 CS2F 6 5 4 L3EA26 3 L3EA25 2 L3EA24 R/W 0 00100 to 00111 CS2C 01100 to 01111 CS2E 10100 to 10111 CS2G 1 L3EA23 0 0 L3EA22 0 11000 to 11111: Set prohibition Figure 3.8.4 MMU Control Register 92C820-141 2007-02-16 TMP92C820 3.8.4 Operational Description Setup bank value and bank use in bank setting register of each local area of LOCAL register in common area. Moreover, in that case, a combination pin is set up and the MEMC simultaneously sets up mapping. When CPU outputs logical address of the local area, MMU outputs physical address to the outside pin according to value of bank setting register. Access of external memory becomes possible therefore. Common area located in each local area should be passed surely when changing BANK. For example, when the program jump BANK0 of LOCAL2 to BANK6, please jump from BANK0 to COMMON2 once and afterwards jump to BANK6. Please do not use as bank that overlaps with another bank since this common area overlaps with either of eight banks of local area on the physical map. Example program is as next page follows. 92C820-142 2007-02-16 TMP92C820 SRAM 8 Mbytes 8 bits CS0 Data/Stack RAM CS0 000000H~1FFFFFH (Logical) 000000H~7FFFFFH (Physical) CS1 Data Address TMP92C820 RD WRLL , WRLU , WRUL , WRUU SRLLB , SRLUB , SRULB , SRUUB : SRAM SDRAM 16 Mbytes 16 bits Display SDRAM CS1 400000H~7FFFFFH (Logical) 000000H~FFFFFFH (Physical) Program ROM MROM 16 Mbytes 16 bits CS2 SDCLK, SDCKE SDLLDQM, SDLUDQM, SDULDRM, SDUUDQM SDCSL , SDCSH , SDRAS , SDCAS , SDWE CS2 C00000H~FFFFFFH (Logical) 000000H~FFFFFFH (Physical) EA24, EA25 Data ROM CS3 MROM 64 Mbytes 16 bits CS3 800000H~BFFFFFH (Logical) 000000H~3FFFFFH (Physical) * In case of 16-bit bus memory, address connection is ...: CPU A1 = Memory A0, CPU A2 = Memory A1... * In case of 8-bit bus memory, address connection is ...: CPU A0 = Memory A0, CPU A1 = Memory A1... Figure 3.8.5 H/W Setting Example At, Figure 3.8.5 it shows example of connection TMP92C820 and some memories: Program ROM: MROM, 16 Mbytes, Data ROM: MROM, 64 Mbytes, Data RAM of 8-bit bus: SRAM, 8 Mbytes, Display RAM: SDRAM, 16 Mbytes. In case of 16-bit bus memory connection, it needs to shift 1-bit address bus from TMP92C820 and 8-bit bus case, direct connection address bus from TMP92C820. In that figure, logical address and physical address are shown. And each memory allot each chip select signal, RAM: CS0 , SDRAM: CS1 , Program MROM: CS2 , Data MROM: CS3 . In case of this example, as data MROM is 64 Mbytes, this MROM connect to EA24 and EA25. Initial condition after reset, because TMP92C820 access from CS2 area, CS2 area allots to program ROM. It can set free setting except program ROM. 2H 92C820-143 2007-02-16 TMP92C820 ; Initial Setting ; CS0 LD LD LD LD ; CS1 LD LD LD LD ; CS2 LD LD LD LD ; CS3 LD LD LD LD ; CSX LD LD ; Port LD LD ~ LDW LD LD ~ LD (MSAR0), 00H (MAMR0), FFH (B0CSL), 22H (B0CSH), 80H (MSAR1), 40H (MAMR1), FFH (B1CSL), 11H (B1CSH), 8DH (MSAR2),C0H (MAMR2), 7FH (B2CSL), 11H (B2CSH), 0C1H (MSAR3), 80H (MAMR3), 7FH (B3CSL), 66H (B3CSH), 81H (BEXCSL), 11H (BEXCSH), 01H (P8FC), 3FH (P8FC2), 02H (P7CR), 1F1FH (PJFC), 0FFH (SDACR), 083H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Logical address area: 000000H to 1FFFFFH Logical address size: 2 Mbytes Condition: WR 3 states (1 wait), RD 3 states (1 wait) SRAM, 8 bits Logical address area: 400000H to 7FFFFFH Logical address size: 4 Mbytes Condition: WR 2 states (0 waits) RD 2 states (0 waits) Condition: SDRAM, 16 bits Logical address area: C00000H to FFFFFFH Logical address size: 4 Mbytes Condition: WR 2 states (0 waits) RD 2 states (0 waits) Condition: ROM, 16 bits Logical address area: 800000H to BFFFFFH Logical address size: 4 Mbytes Condition: WR 5 states (3 waits), RD 5 states (3 waits) Condition: ROM,16 bits ; Condition: WR 2 states (0 waits), RD 2 states (0 waits) ; Condition: 16 bits ; CS0 to CS3 , EA24, EA25: port 8 setting ; CS1 SDCSL setting ; WRUU , WRUL , WRLU , WRLL , RD ; PJ<7:0> = SDRAM control ; Add-MUX select type B, SDRAM, auto init enable SDRAM setup time ; Interval refresh (SDRCR), 01H Figure 3.8.6 Bank Operation S/W Example 1 Secondly, it shows example of initial setting at Figure 3.8.6. Because CS0 connect to RAM: 8-bit bus, 8 Mbytes, it need to set 8-bit bus. At this example, it set 3 states setting. In the same way CS1 set to 16-bit bus and 2 states, CS2 set 16-bit bus and 2 states, CS3 set 16-bit bus and 5 states. By MEMC controller, each chip selection signal's memory size, don't set actual connect memory size, need to set that logical address size: fitting to each local area. Actual physical address is set by each area's BANK register setting. CSEX setting of MEMC is except above CS0 to CS3's setting. This program example isn't used CSEX setting. Finally pin condition is set. Ports 80 to 85 set to CS0 , CS1 , CS2 , CS3 , EA24, EA25, and SDRAM condition. 3H 92C820-144 2007-02-16 TMP92C820 ; Bank Operation ; ***** CS2 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H ORG 800000H ORG a00000H ORG c00000H ORG E00000H ; ; ; ; ; ; ; Program ROM: Start address at BANK0 of LOCAL2 Program ROM: Start address at BANK1 of LOCAL2 Program ROM: Start address at BANK2 of LOCAL2 Program ROM: Start address at BANK3 of LOCAL2 Program ROM: Start address at BANK4 of LOCAL2 Program ROM: Start address at BANK5 of LOCAL2 Program ROM: Start address at BANK6 of LOCAL2 LD (LOCAL3), 85H LDW HL, (800000H) LD (LOCAL3), 88H LDW BC, (800000H) ~ ORG ; Program ROM: Start address at BANK7 (= COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH ; LOCAL3 BANK5 set 14xxxxH ; Load data (5555H) form BANK5 (140000H: Physical address) of LOCAL3 ( CS3 ) ; LOCAL3 BANK8 set 20xxxxH ; Load data (AAAAH) form BANK8 (200000H: Physical address) of LOCAL3 ( CS3 ) ; Program ROM: End address at BANK7 (= COMMON2) of LOCAL2 FFFFFFH ; ***** ORG ORG ORG ORG ORG ORG ~ ORG ORG ORG ~ ORG ORG ORG ORG ORG ORG ORG ORG CS3 ***** 0000000H 0400000H 0800000H 0C00000H 1000000H 1400000H dw 5555H 1800000H 1C00000H 2000000H dw AAAAH 2400000H 2800000H 2C00000H 3000000H 3400000H 3800000H 3C00000H 3FFFFFFH ; ; ; ; ; ; Data ROM: Start address at BANK0 of LOCAL3 Data ROM: Start address at BANK1 of LOCAL3 Data ROM: Start address at BANK2 of LOCAL3 Data ROM: Start address at BANK3 of LOCAL3 Data ROM: Start address at BANK4 of LOCAL3 Data ROM: Start address at BANK5 of LOCAL3 ; Data ROM: Start address at BANK6 of LOCAL3 ; Data ROM: Start address at BANK7 of LOCAL3 ; Data ROM: Start address at BANK8 of LOCAL3 ; ; ; ; ; ; ; ; Data ROM: Start address at BANK9 of LOCAL3 Data ROM: Start address at BANK10 of LOCAL3 Data ROM: Start address at BANK11 of LOCAL3 Data ROM: Start address at BANK12 of LOCAL3 Data ROM: Start address at BANK13 of LOCAL3 Data ROM: Start address at BANK14 of LOCAL3 Data ROM: Start address at BANK15 of LOCAL3 Data ROM: End address at BANK15 of LOCAL3 Figure 3.8.7 Bank Operation S/W Example 2 Here shows example of data access between one BANK and other BANK. Figure 3.8.7 is one software example. A dot line square area shows one memory and each dot line square shows CS2 's program ROM and CS3 's data ROM. Program start from E00000H address, firstly, write to BANK register of LOCAL3 area upper 5-bit address of access point. In case of this example, because most upper address bit of physical address is EA25, most upper address bit of BANK register is meaningless. 4 bits of upper 5 bits address means 16 BANKs. After setting BANK5, accessing 800000H to BFFFFFH address: Logical LOCAL3 address, actually access to physical 1400000H to 1700000H address. 4H 92C820-145 2007-02-16 TMP92C820 ; Bank Operation ; ***** CS2 ***** ORG 000000H ORG 200000H NOP ~ JP E00100H ORG 400000H ORG 600000H NOP ~ JP E00200H ORG 800000H ORG a00000H ORG c00000H !!!! Program Start !!!! ORG E00000H ; Program ROM: Start address at BANK0 of LOCAL2 ; Program ROM: Start address at BANK1 of LOCAL2 ; Operation at BANK1 of LOCAL2 ; ; ; ; ; ; ; ; Jump to BANK7 (= COMMON2) of LOCAL2 Program ROM: Start address at BANK2 of LOCAL2 Program ROM: Start address at BANK3 of LOCAL2 Operation at BANK3 of LOCAL2 Jump to BANK7 (= COMMON2) of LOCAL2 Program ROM: Start address at BANK4 of LOCAL2 Program ROM: Start address at BANK5 of LOCAL2 Program ROM: Start address at BANK6 of LOCAL2 LD JP ~ ORG (LOCAL2), 81H C00000H ; Program ROM: Start address at BANK7 (= COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH ; LOCAL2 BANK1 set 20xxxxH ; Jump to BANK1 (200000H: Physical address) of LOCAL2 E00100H LD (LOCAL2), 83H JP C00000H E00200H LD (LOCAL1), 00H LD (LSARCH), 60H LD (LSARCM), 00H LD (LSARCL), 00H SET 0, (LCTCTL) FFFFFFH ; LOCAL2 BANK3 set 60xxxxH ; Jump to BANK3 (600000H: Physical address) of LOCAL2 ~ ORG ~ ORG ; ; ; ; ; ; ; Disable Bank! LCD display set C_area start address C_area start address C_area start address LCD Display start Program ROM: End address at BANK7 (= COMMON2) of LOCAL2 ; ***** ORG ORG ORG ORG ~ ORG ORG ORG ORG ORG CS1 ***** 000000H 200000H 400000H 600000H dl 01234567H ; ; ; ; ; SDRAM: Start address at BANK0 of LOCAL1 SDRAM: Start address at BANK1 of LOCAL1 SDRAM: Start address at BANK2 of LOCAL1 SDRAM: Start address at BANK3 (= COMMON1) of LOCAL1 display data 800000H a00000H c00000 E00000H FFFFFFH ; ; ; ; ; SDRAM: Start address at BANK4 of LOCAL1 SDRAM: Start address at BANK5 of LOCAL1 SDRAM: Start address at BANK6 of LOCAL1 SDRAM: Start address at BANK7 of LOCAL1 SDRAM: End address at BANK7 of LOCAL1 Figure 3.8.8 Bank Operation S/W Example 3 92C820-146 2007-02-16 TMP92C820 At Figure 3.8.8, it shows example of program jump. In the same way with before example, two dot line squares show each CS2 's program ROM and CS1 's (SDCS) SDRAM. Program start from E00000H common address, firstly, write to BANK register of LOCAL2 area upper 3-bit address of jumping point. After setting BANK1, jumping C00000H to DFFFFFH address: Logical LOCAL2 address, actually jump to physical 200000H to 3FFFFFH address. When return to common area, it can only jump to E00000H to FFFFFFH without writing to BANK register of LOCAL2 area. By a way of setting of BANK register, the setting that BANK address and common address conflict with is possible. When two kinds or more logical addresses to show common area exist, management of BANK is confused. We recommends not to use the BANK setting, BANK address and common address conflict with. Please set similarly when jumping through CS . After setting BANK4, jumping 400000H to 5FFFFFH address: Logical local area of CS1 , actually jump to physical 800000H to 9FFFFFH address. When using LCD display data for SDRAM, we recommend setting display area to common area in SDRAM. Because of, LCD displays DMA occurs at synchronous less. If SDRAM bank is change; you don't need to care only common area. It is a mark paid attention to here, it needs to go by way of common area by all means when moves from a bank to a bank. In other words, it must write to BANK register only in common area and it prohibits writing the BANK registers in BANK area. If it modify the BANK register's data in BANK area, program run away. Please do not set bank function of MMU as display RAM. This is because reading LCDC display data is not controlled by the CPU. Therefore if BANK of display area is changed during LCD displaying, it cannot display. It is recommended to allocate display data to a common area. 5H 92C820-147 2007-02-16 TMP92C820 3.9 Serial Channels (SIO) The TMP92C820 includes three serial I/O channels. For each channel either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. (Channel 2 can be selected only UART mode.) * I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. Mode 1: 7-bit data * UART mode Mode 2: 8-bit data Mode 3: 9-bit data In mode 1 and mode 2 a parity bit can be added. Mode 3 has a wakeup function for making the master controller start slave controllers via a serial link (Multi-controller system). Figure 3.9.2, Figure 3.9.3, and Figure 3.9.4 are block diagrams for each channel. Each channel can be used independently. Each channel operates in the same fashion except for the following points; hence only the operation of channel 0 is explained below. 0H 1H 2H Table 3.9.1 Differences between Channels 0 to 2 Channel 0 Pin name TXD0 (PF0) RXD0 (PF1) CTS0 /SCLK0 (PF2) Yes Channel 1 TXD1 (PF3) RXD1 (PF4) CTS1 /SCLK1 (PF5) No Channel 2 TXD2 (P95) RXD2 (P96) No IrDA mode This chapter contains the following sections: 3.9.1 Block Diagrams 3.9.2 Operation for Each Circuit 3.9.3 SFRs 3.9.4 Operation in Each Mode 3.9.5 Support for IrDA 3H 4H 5H 6H 7H 8H 9H 10H 1H 12H 92C820-148 2007-02-16 TMP92C820 * Mode 0 (I/O interface mode) Bit0 1 2 3 4 5 6 7 Transfer direction * Mode 1 (7-bit UART mode) No parity Parity Start Start Bit0 Bit0 1 1 2 2 3 3 4 4 5 5 6 6 Stop Parity Stop * Mode 2 (8-bit UART mode) No parity Parity Start Start Bit0 Bit0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Stop Parity Stop * Mode 3 (9-bit UART mode) Start Wakeup Start Bit0 Bit0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 Bit8 Stop Stop When bit8 = 1, address (Select code) is denoted. When bit8 = 0, data is denoted. Figure 3.9.1 Data Formats 92C820-149 2007-02-16 TMP92C820 3.9.1 Block Diagrams Prescaler T0 2 4 8 16 32 64 T2 T8 T32 Serial clock generation circuit BR0CR Selector UART mode Selector SIOCLK BR0CR SC0MOD0 SCLK0 IN (Shared with PF2) I/O interface mode SCLK0 OUT (Shared with PF2) I/O interface mode SC0CR CTS0 Receive counter SC0MOD0 (UART only / 16) (Shared with PF2) RXD0 (Shared with PF1) Receive buffer 1 (Shift register) RB8 Receive buffer 2 (SC0BUF) Error flag TB8 Transmission buffer (SC0BUF) SC0CR TXD0 (Shared with PF0) Figure 3.9.2 Block Diagram of Serial Channel 0 92C820-150 2007-02-16 TMP92C820 Prescaler T0 2 4 8 16 32 64 T2 T8 T32 Serial clock generation circuit BR1CR Selector UART mode Selector SIOCLK BR1CR SC1MOD0 SCLK1 IN (Shared with PF5) I/O interface mode SCLK1 OUT (Shared with PF5) I/O interface mode SC1CR (UART only / 16) Receive counter SC1MOD0 TXDCLK Transmission control SC1CR CTS1 (Shared with PF5) RXD1 (Shared with PF4) Receive buffer 1 (Shift register) Parity control RB8 Receive buffer 2 (SC1BUF) Error flag TB8 Transmission buffer (SC1BUF) SC1CR TXD1 (Shared with PF3) Figure 3.9.3 Block Diagram of Serial Channel 1 92C820-151 2007-02-16 TMP92C820 Prescaler T0 2 4 8 16 32 64 T2 T8 T32 Serial clock generation circuit BR2CR Selector UART mode Selector SIOCLK BR2CR SC2MOD0 SCLK1 IN (Shared with PF5) I/O interface mode SC2CR Receive buffer 1 (Shift register) Serial channel interrupt control Transmision counter (UART only / 16) TXDCLK Transmission control RXD2 (Shared with P96) Parity control RB8 Receive buffer 2 (SC2BUF) Error flag TB8 Transmission buffer (SC2BUF) SC2CR |